A 4.8-µVrms-noise CMOS-MEA with Density-Scalable Active Readout Pixels via Disaggregated Differential Amplifier Implementation
Jun
Ogi1*,
Yuri
Kato1,
Yusaku
Nakashima2,
Motoko
Jingu1,
Yoshihisa
Matoba1,
Naohiko
Kimizuka1,
Chigusa
Yamane1,
Masataka
Maehara1,
Takuya
Kishimoto2,
Shigeki
Hashimoto2,
Eriko
Matsui2 and
Yusuke
Oike1
-
1
Sony Semiconductor Solutions Co., Ltd., Research Division, Japan
-
2
Sony (Japan), Biomedical Research Department, R&D Platform, Japan
Abstract
We demonstrate a 4.8-µVrms noise CMOS-MEA based on the active-pixel-sensors readout technique with disaggregated differential amplifier implementation. Circuit elements of the differential amplifier are divided into a readout pixel, a reference pixel, and a column circuit. This disaggregation contributes to the smaller area of the readout pixel, which is less than 81 μm2. We observed neuron signals around 100 μV with a fabricated prototype chip. The implementation has technological feasibility of up to 12-μm-pitch electrode density and 6,912 readout channels for high-spatial resolution mapping of neuron network activity.
I. Introduction
In previous decades, a CMOS-based Microelectrode Array (MEA) was introduced to achieve two-dimensional high spatial resolution mapping of action potentials (APs)[1, 2]. The high resolution mapping of APs in neuron cells can reveal answers to questions regarding the complexities of neuron network activities.
To understand the network activity better, both readout channel numbers and electrode density must increase further while maintaining sufficiently low noise levels (less than 10 μVrms). Readout techniques with active pixel sensors (APS) have been proposed to increase the channel number to over ten thousand, the electrode density is limited avobe a 30 μm electrode pitch because of the large area of the readout circuits integrated under the each electrode[3, 4]. We present scalability for a higher-density and larger channel number CMOS-MEA[5]. However, the noise level was not sufficiently low to observe the neuron APs.
In this paper, we demonstrate a 4.8-μVrms noise CMOS-MEA based on the APS readout technique with disaggregated differential amplifier implementation method. This has the technological feasibility for high-density electrode integration with 12-µm pitch electrode density and 6,912 readout channels.
II. Implementation
In order to reduce noise in the readout channel of CMOS-MEAs, the channel is usually equipped with a large input capacitance, a low-noise and high-gain differential amplifier, and a band pass filter[2]. In previous works for sub-10 μVrms readout noise using the APS, these circuit elements were integrated under each electrode, increasing the readout pixel area[3]. Figure 1(a) shows the readout implementation of this work. The circuit elements in the differential amplifier are divided into a readout pixel, a reference pixel and a column circuit. The sensing electrode, which can sense cell AP, directly connects to the input amplifier in the readout pixel. In the reference pixel, the input amplifier connects to the ground via an input capacitance. The direct connection of the readout pixel can increase input signal level at the amplifier gate, while the input capacitance in the reference pixel controls the gain and dynamic range for optimized level. The disaggregated differential amplifier implementation can reduce the readout pixel area due to the reduced circuit elements in the pixel.
Single slope analogue to digital converters (ADCs) has advantages of high-speed data conversion through the use of a high-speed input clock[6] and performs 48-ksps high-speed analogue-to-digital conversion with 12-bit resolution. The eight row and 54 column readout pixels connect to 432 column circuits one by one. The 48 ksps over sampling compared with signal band of the neuron AP (AP band) contributes to reduce folding noise in the ADC.
Figure 1(b) shows a fabricated prototype chip with a 0.14-μm CMOS process. The column circuit pitch is 12 μm and the readout electrode pitch is 96 μm. Although the electrode pitch is limited by the limited number of the column circuit, the readout circuit area in each pixel is less than 81 μm2. This is much smaller than the 450 μm2 in the previous two-stage amplifier implementation[4].
III. Measurement results
Input-referred noise on the readout channels in the prototype CMOS-MEA reduced to 4.75 μVrms after post-processing of the frequency band limitation to the AP band (from 300 Hz to 3.3 kHz) by digital finite response (FIR) filters. The intrinsic noise without FIR filtering reduced to 12.8 μVrms by the disaggregated differential amplifier implementation. In addition, the noise after filtering further reduced by the over sampling in the ADCs and is proportional to the inverse of the readout sampling rate, as shown in Fig. 2(a).
Figure 2(b) is a composited optical micrograph of a visible and fluorescent imaging of the neuron cells cultured on the prototype chip. Figure 2(c)-(e) show the AP signals that were observed with electrodes marked in Fig. 2(b). Neuron AP signals of about 100 μV peak level were clearly recognized because of the low readout noise. These results show the feasibility of our CMOS-MEA technology for neuron AP measurement.
IV. Scalability
The electrode density and the channel number can be made higher and larger by increasing the ADCs number and pixel multiplication factor for each ADC because of the small readout pixel area and small column pitch in the CMOS-MEA technology proposed in this work.
In case of four-tier ADCs (1,728 ADCs) on both sides of the pixel array and four times multiplication (12 kfps frame rate), the electrode pitch will be decreased proportionally to the column pitch (12 μm), with 6,912 readout channels (16 rows and 432 columns). The AP band noise is still less than 10 μVrms (8.8 µVrms) while the four times multiplication will increase the readout noise. Furthermore, introducing advanced processes for ADCs can increase the channel number because the ADC pitch can decrease and the sampling speed can increase.
IV. Conclusion
We introduce the disaggregated differential amplifier implementation that can reduce the circuit area of the readout pixel in CMOS-MEA with APS readout technique. The prototype chip with the implementation demonstrated a 4.8-µVrms readout noise and observation of neuron AP at about a 100 μV signal level. This implementation concept is scalable for high spatial resolution mapping of neuron network activity.
References
[1] B. Eversmann et al., IEEE J. SSC 38, 2306 (2003)
[2] M.Barrini et al., IEEE J. SSC 49, 2705 (2014)
[3] B. Johnson et al., Proc. IEEE BioCAS 2013, p. 109 (2013)
[4] Huys et al., Lab Chip 12, 1274 (2012)
[5] J. Ogi et al., Biointerphases 12, 05F402 (2017)
[6] H. Wakabayashi et al., Proc. IEEE ISSCC 2010, 22.9 (2010)
Keywords:
high-density CMOS-based MEAs,
Neuron Action Potentials,
CMOS circuits design,
Noise Reduction,
scalable hardware architecture
Conference:
MEA Meeting 2018 | 11th International Meeting on Substrate Integrated Microelectrode Arrays, Reutlingen, Germany, 4 Jul - 6 Jul, 2018.
Presentation Type:
Oral Presentation
Topic:
Microelectrode Array Technology
Citation:
Ogi
J,
Kato
Y,
Nakashima
Y,
Jingu
M,
Matoba
Y,
Kimizuka
N,
Yamane
C,
Maehara
M,
Kishimoto
T,
Hashimoto
S,
Matsui
E and
Oike
Y
(2019). A 4.8-µVrms-noise CMOS-MEA with Density-Scalable Active Readout Pixels via Disaggregated Differential Amplifier Implementation.
Conference Abstract:
MEA Meeting 2018 | 11th International Meeting on Substrate Integrated Microelectrode Arrays.
doi: 10.3389/conf.fncel.2018.38.00091
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Received:
15 Mar 2018;
Published Online:
17 Jan 2019.
*
Correspondence:
Dr. Jun Ogi, Sony Semiconductor Solutions Co., Ltd., Research Division, Kanagawa, 243-0014, Japan, Jun.Ogi@sony.com