Cancellation of the stimulation artifacts by stimulus-dependent nanoampere correction pulses
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1
AGH University of Science and Technology, Department of Particle Interactions and Detection Techniques, Poland
Motivation
Electrical stimulation of neurons often make recording of the neuronal response difficult. The artifact voltage at the stimulating electrode can reach hundreds of millivolts, while the amplitude of the recorded spikes are in sub-millivolt range. Due to the complex nature of the electrode impedance, the artifact lasts for several milliseconds following the stimulation pulse, making the detection of the of low-latency spikes from directly activated neurons at the stimulating electrodes specifically challenging. The problem was partially solved before by modification of the stimulation pulse waveform [1], but ultimately the current waveform should be optimized for stimulation efficacy rather than for artifacts.
Here we propose a novel approach to reduction of the artifact based on low-amplitude correction pulse applied to the stimulating electrode after the stimulation pulse. The correction pulse generates its own artifact that compensates the artifact remaining at the electrode after the stimulation pulse. The goal is to record activity from the stimulated neuron, at the stimulating electrode, while the correction pulse is being generated.
We plan to use this method in experiments based on our new dedicated integrated circuit designed for simultaneous stimulation and recording of neuronal activity [2]. According to simulations, our method will allow to record neuronal signals at the stimulating electrode with minimal latency (less than 50 µs) for standard biphasic shape of the stimulation pulse.
Material and Methods
To estimate correctly the stimulation artifact shape and to design optimal correction pulse, one must know the impedance of the concrete electrode used for measurement. In experimental practice the electrode impedance will be measured using on-chip stimulation and recording circuitry. The measurements will be fitted to three-element equivalent circuit of the electrode impedance (Fig. 1) and the parameters of the model will be used to design the correction pulse.
For numerical simulations, we used existing measurements of a platinum black microelectrode with 5 µm diameter. Since the electrochemical resistance for this electrode is expected to be in GΩ range, we ignored it for our calculations. We used symmetric biphasic stimulation pulse with 100 µs per phase duration and amplitude of 1 µA, which is in the upper range of amplitudes used in similar experiments [1,3]. We built numerical model of the artifact and designed the correction pulse by deconvolution of the post-pulse artifact with respect to the electrode impulse response.
For the method verification we performed simulations in Cadence (VLSI design environment) using schematic of the stimulation & recording circuitry of the NSR64 ASIC [2], and realistic model of the electrode impedance based on 26-element equivalent circuit [4] to model the electrical properties of double layer (Fig. 1).
Results
There are two main factors that can limit efficacy of our method. First, electrode impedance is in general nonlinear. However, as the electrode voltages should not exceed 200 mV during stimulation (for the 5 µm platinum black electrode and up to 2 µA current pulses) the nonlinearity effects are expected to be very limited, although this must be confirmed in our experimental system.
Second, limited resolution of the stimulation circuitry will affect the shape of the correction pulse. In case of the NSR64 chip, the stimulation current is defined by two digital-to-analog converters (7-bit and 4-bit, plus polarity bit). The chip can generate 64 independent stimulation signals with temporal resolution of 25 µs. Alternatively, the temporal resolution can be improved if fewer channels are used for stimulation, reaching 2.5 µs for one active channel. We analyzed the artifact amplitude at the output of the recording amplifier to take into account its low-pass filtering properties. The gain of the amplifier was set to 250 and the first-order low-pass filter was set to 10 kHz. The amplifier input was disconnected from the electrode for the duration of the biphasic stimulation pulse by a CMOS switch. The influence of amplitude resolution of the NSR64 ASIC (7 nA) was minor (data not shown). The effect of temporal resolution was more obvious (Fig. 2). Although the artifact at the amplifier input reached 5 mV peak-to peak, its spectrum is dominated by high-frequency components. Therefore, the artifact at the amplifier output was only 150 mV peak-to-peak when measured for latencies above 25 µs. In comparison, the output linear range of the amplifier is 2V peak-to-peak.
Discussion
The artifact reduction method proposed here provides promising results in numerical simulations. We hope it will allow to detect stimulated spikes with <50 µs latencies, for stimulation amplitudes up to a few microamps and various pulse waveforms – at least in experimental conditions similar to that of our previous work [1,3]. We are currently testing the resistance of the algorithm to imperfections of the electrode impedance measurements. The NSR64 ASIC is currently in electrical tests and the experimental validation of our algorithm should start in May.
Figure legend
Figure 1. Model of the electrode impedance used in this work. (a) The equivalent electrical circuit. CPE – Constant Phase element, Re – electrochemical resistance, Rs – spread resistance. (b) The 26-element model of the CPE impedance. (c) Module of the electrode impedance.
Figure 2. Proposed artifact cancellation method simulated with the NSR64 ASIC. (a) Shape of the stimulation current. The biphasic pulse starts at 100 µs and ends at 300 µs. (b) Artifact at the amplifier input. (c) Artifact at the amplifier output.
Acknowledgements
This work is supported by Polish National Science Centre (grant 2013/10/M/NZ4/00268).
References
[1] Hottowy P., et al., Properties and application of a multichannel integrated circuit for low-artifact, patterned electrical stimulation of neural tissue, Journal of Neural Engineering 9 (6), pp. 1–17, 2012.
[2] Szypulska M., et al., Modular ASIC-based system for large-scale electrical stimulation and recording of brain activity in behaving, Mixed Design of Integrated Circuits and Systems, 23rd International Conference, pp. 217–222, MIXDES 2016
[3] Jepson L.H., et al., Focal electrical stimulation of major ganglion cell types in the primate retina for the design of visual prostheses, Journal of Neuroscience 33 (17), pp. 7194-7205, 2013.
[4] Gonzalez E., et al., Conceptual design of a selectable fractional-order differentiator for industrial applications, Fractional Calculus Appl. Anal. 17 (3), pp. 697–716, 2014.
Keywords:
stimulation artifact,
electrode impedance,
Numerical modeling,
Integrated Circuit,
CMOS
Conference:
MEA Meeting 2018 | 11th International Meeting on Substrate Integrated Microelectrode Arrays, Reutlingen, Germany, 4 Jul - 6 Jul, 2018.
Presentation Type:
Poster Presentation
Topic:
Stimulation strategies
Citation:
Kołodziej
K,
Dąbrowski
W and
Hottowy
P
(2019). Cancellation of the stimulation artifacts by stimulus-dependent nanoampere correction pulses.
Conference Abstract:
MEA Meeting 2018 | 11th International Meeting on Substrate Integrated Microelectrode Arrays.
doi: 10.3389/conf.fncel.2018.38.00122
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Received:
18 Mar 2018;
Published Online:
17 Jan 2019.
*
Correspondence:
Dr. Paweł Hottowy, AGH University of Science and Technology, Department of Particle Interactions and Detection Techniques, Kraków, 30-059, Poland, hottowy@agh.edu.pl