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Advances in Porous Semiconductor Research

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Front. Chem. | doi: 10.3389/fchem.2018.00582

High Anodic-Voltage Focusing of Charge Carriers in Silicon Enable the Etching of Regularly-Arranged Submicrometer Pores at High Density and High Aspect-Ratio

Chiara Cozzi1, Giovanni Polito1, Lucanos M. Strambini2 and  Giuseppe Barillaro1, 2, 3*
  • 1Dipartimento di Ingegneria dell'Informazione, Università degli Studi di Pisa, Italy
  • 2Istituto di elettronica e di ingegneria dell'informazione e delle telecomunicazioni (IEIIT), Italy
  • 3Università degli Studi di Pisa, Italy

The anodic dissolution of silicon in acidic electrolytes is a well-known technology enabling the silicon machining to be accurately controlled down to the micrometer scale in low-doped n-type silicon electrodes. Attempts to scale down this technology to the submicrometer scale has shown to be challenging, though it premises to enable the fabrication of meso and nanosystems that would greatly impact the fields of biosensors and nanomedicine.
In this work, we report on the electrochemical etching at high anodic voltages (up to 40 V) of two-dimensional regular arrays of millions pores per square centimeter (up to 30 × 106 cm-2) with sub-micrometric diameter (down to ~850 nm), high depth (up to ~40 µm), and high aspect ratio (up to ~45) using n-type low-doped n-type silicon electrodes (resistivity 3-8 Ω cm). The use of high anodic voltages, which is over one order of magnitude higher than commonly used anodic voltage values, enable to tremendously improves hole focusing at the pore tips during the etching and, in turn, to control of electrochemical etching of submicrometer-sized pores when spatial period reduces below 2 μm. A theoretical model allows experimental results to be interpreted in terms of an electric-field-enhanced focusing of holes at the tip apex of the pores at high anodic voltages, with respect to the pore base, which leads to a smaller curvature radius of the tip apex and enables, in turn, the etching of pore tips to be preferentially sustained over time and space.

Keywords: nanostructuring, anodization, porous silicon, Submicrometer pores, carrier focusing, High Voltage

Received: 21 Sep 2018; Accepted: 08 Nov 2018.

Edited by:

Thierry Djenizian, École des Mines de Saint-Étienne - Campus Georges Charpak Provence, France

Reviewed by:

Luca De Stefano, Istituto per la Microelettronica e Microsistemi, Consiglio Nazionale delle Ricerche, Italy
Lluis F. Marsal, University of Rovira i Virgili, Spain  

Copyright: © 2018 Cozzi, Polito, Strambini and Barillaro. This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) and the copyright owner(s) are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.

* Correspondence: Prof. Giuseppe Barillaro, Università degli Studi di Pisa, Pisa, Italy, g.barillaro@iet.unipi.it