Breakdown-limited endurance in HZO FeFETs: mechanism and improvement under bipolar stress

Breakdown is one of main failure mechanisms that limit write endurance of ferroelectric devices using hafnium oxide-based ferroelectric materials. In this study, we investigate the gate current and breakdown characteristics of Hf0.5Zr0.5O2/Si ferroelectric field-effect transistors (FeFETs) by using carrier separation measurements to analyze electron and hole leakage currents during time-dependent dielectric breakdown (TDDB) tests. Rapidly increasing substrate hole currents and stress-induced leakage current (SILC)-like electron currents can be observed before the breakdown of the ferroelectric gate insulator of FeFETs. This apparent degradation under voltage stress is recovered and the time-to-breakdown is significantly improved by interrupting the TDDB test with gate voltage pulses with the opposite polarity, suggesting that defect redistribution, rather than defect generation, is responsible for the trigger of hard breakdown.


Introduction
HfO2-based ferroelectric thin films have been actively employed in recent electron device research thanks to their CMOS compatibility, established know-how on the fabrication process, and high scalability of thickness to 10 nm or lower (Böscke et al., 2011a;Müller et al., 2012;Park et al., 2015;Migita et al., 2018b;Kim et al., 2018;Tan et al., 2021;Toprasertpong et al., 2022a;Schroeder et al., 2022). Ferroelectric field-effect transistors (FeFETs) with HfO2-based ferroelectric thin films as gate insulators have received considerable attention, not only because of the maturity of the HfO2 deposition technology in the advanced transistor process, but also because of their low energy consumption, high speed, and satisfactory retention during their operation. HfO2-based FeFETs have been investigated as promising devices for low-power nonvolatile memory (Böscke et al., 2011b;Trentzsch et al., 2016;Dünkel et al., 2017;Florent et al., 2018a;Müller et al., 2021) and non-von Neumann computing applications Dutta et al., 2022;Matsui et al., 2021;Luo et al., 2022;Toprasertpong et al., 2022b).
Despite their excellent properties, one of the most crucial issues to be dealt with towards the practical use of HfO2-based FeFETs is the write endurance. There are two major mechanisms that have been reported to determine the write endurance of FeFETs: the memory window narrowing and gate dielectric breakdown. The memory window narrowing refers to a phenomenon where a separation of the threshold voltages of the two states (high and low threshold voltage states) becomes gradually smaller and eventually becomes zero after certain operating cycles. The polarization states are no longer able to be read out through threshold voltages and FeFETs lose a capability as memory devices. On the other hand, gate dielectric breakdown refers to a situation where the gate insulator experiences hard breakdown under a certain amount of electrical stress. Hard breakdown makes gate insulators conductive, electrically connects the gate and channel, and causes FeFETs to lose their function as field-effect transistors.
Memory window narrowing and gate dielectric breakdown originate from different physics and occur almost independently; therefore, the write endurance of FeFETs, i.e. a number of write operations before failure, is determined by the mechanism that leads to earlier failure. The dominant mechanism depends on the device property and the operation scheme of each specific device and application. Write endurance of state-of-the-art FeFETs is typically dominated by the memory window narrowing (Böscke et al., 2011b;Yurchuk et al., 2016;Trentzsch et al., 2016;Dünkel et al., 2017;Florent et al., 2018a;Gong et al., 2018) because of the presence of large density of trapped charges in the vicinity of the interfacial layer (IL) between HfO2 and Si (Toprasertpong et al., 2019;Toprasertpong et al., 2020a), while there are only a few reports showing that endurance of FeFETs is limited by gate dielectric breakdown Peng et al., 2021). That is, the FeFET operation so far usually reaches failure because of memory window narrowing before gate dielectric breakdown occurs; thus, there is still a poor understanding of the gate dielectric breakdown mechanism in HfO2-based FeFETs. On the other hand, a lot of effort has been put on the material and device-structure engineering such that there have already been some reports in recent years demonstrating FeFET memory devices with remarkably suppressed memory window narrowing (Sharma et al., 2020;Yan et al., 2020;Tan et al., 2021;Liao et al., 2022). In such devices with suppressed memory window narrowing, gate dielectric breakdown may become a dominant mechanism that limits write endurance and play a crucial role in device reliability. Furthermore, there are some applications of FeFETs using new-concept computing that are insensitive to memory window narrowing, such as reservoir computing (Nako et al., 2022). In such applications, gate dielectric breakdown will be a dominant endurance-limiting mechanism. Therefore, gaining an understanding of the mechanism of gate dielectric breakdown is important to improve the overall write endurance characteristics of HfO2based FeFETs.
In this study, we investigate the breakdown characteristics and the stress-induced degradation behavior as well as the underlying physical mechanism in Hf0.5Zr0.5O2 (HZO)/IL/Si FeFETs. The carrier separation measurement and interrupted stress for time-dependent dielectric breakdown (TDDB) evaluation are employed to analyze the physical mechanism underlying gate dielectric breakdown.

Sample Preparation
The process flow is shown in Figure 1A. We fabricated n-channel non-ferroelectric FETs (called here as nonferro-FET) with a paraelectric HfO2 gate insulator and FeFETs with a ferroelectric HZO gate insulator on p-type Si substrates with a moderate doping concentration of 4×10 15 cm -3 . After the source and drain (S/D) regions were doped by phosphorus ion implantation and annealed to activate dopants, the Si substrates were cleaned by hydrochloric-peroxide mixture (HPM)-last cleaning process to grow a high-quality SiO2 IL (Toprasertpong et al., 2020). For FeFETs, 10-nm-thick ferroelectric HZO was deposited by atomic layer deposition (ALD) using at using tetrakis(ethylmethylamino)hafnium (TEMAH), tetrakis(ethylmethylamino)zirconium (TEMAZ), and H2O at 300°C. For nonferro-FETs, 10-nm-thick HfO2 was deposited in a similar way but without TEMAZ. TiN was deposited as gate metal by sputtering and Al:Si was deposited as S/D contacts by thermal evaporation. Samples were annealed at 400°C for 30 s in a N2 atmosphere to crystalized the ferroelectric phase in FeFETs. The nonferro-FETs were also annealed at the same condition. Except the ALD step, both samples were processed simultaneously in the same chamber to ensure the same device condition. Figures. 1B and 1C show transmission electron microscopic (TEM) images of the gate stacks of a nonferro-FET and a FeFET, respectively, indicating that HZO was crystallized whereas HfO2 remained amorphous. The IL thickness was similar in the both samples.

Band diagram and breakdown position
Before we discuss the experimental results of the leakage and breakdown behaviors, we examine the band diagram of the HZO (10 nm)/IL (0.7 nm)/Si gate stack and the possible gate leakage path. Figure 2A depicts an example of an ideal band diagram of the HZO/IL/Si gate stack at 3 V when HZO has ferroelectric polarization of 10 µC/cm 2 . Due to high ferroelectric polarization, most literature considers a band diagram with a strong electric field across the IL, which significantly pulls down the band position HZO, as shown in Figure 2A Yurchuk et al., 2016;Gong et al., 2018;Peng et al., 2021;Mulaosmanovic et al., 2021). In such a case, the breakdown of the IL is supposed to determine the gate dielectric breakdown of FeFETs. However, it has been reported that a large density of trapped charges near the HZO/IL interface electrically screens the polarization and suppresses the electric field across the IL (Toprasertpong et al., 2019;Toprasertpong et al., 2022c). Figure 2B depicts the band diagram with ferroelectric polarization of 10 µC/cm 2 and 90% (Ichihara et al., 2020) of induced electrons are trapped at the HZO/IL interface. It can be seen that the band of HZO is not at such a low energy position. This fact indicates that electrons have to tunnel through a thick HZO layer and thus the breakdown of HZO is necessary to describe the gate breakdown failure of FeFETs.

Device characteristics
The I-Vg characteristics of the nonferro-FET and FeFET are shown in Figures 3A and 3B, respectively, for gate current Ig, drain current Id, source current Is, and substrate current Isub. A gate length L is 10 µm and a gate width W is 100 µm. As expected, the nonferro-FET exhibits the Id-Vg characteristics with clockwise hysteresis, which is a feature of electron trapping during Vg scans. On the other hand, the FeFET exhibits counterclockwise hysteresis, which is a feature of ferroelectricity, with a memory window of approximately 1.8 V. Comparison of the I-Vg characteristics of the nonferro-FET and FeFET indicates interesting features on Ig and Isub. Gate current Ig in the HZO FeFET is much larger by several orders of magnitude than in nonferro-FETs having HfO2 with a similar physical thickness. This can be understood from the fact that the poly-crystallinity and a lot of defects such as oxygen vacancies in HZO can promote the gate leakage current, as shown in Figure  3C. It is also found that the substrate current Isub in the FeFET rapidly increases by four orders of magnitude in a narrow range of Vg = 3.6 V to 4.0 V during the forward Vg scan, which is in the same range that Ig also increases rapidly by two orders of magnitude. This finding suggests that a study of the behavior of Isub would be helpful in understanding the behavior of the gate leakage and gate dielectric degradation. The nonferro-FET in Figure 3A does not exhibit this Isub behavior.

Carrier Separation Measurements
Carrier separation measurements (Eitan et al., 1983;Weinberg et al., 1985) were carried out to analyze the behavior of gate leakage and gate dielectric degradation. The electrical measurement tool (Keysight B1500A with high-resolution source/monitor unit modules) was connected with FETs in a way shown in Figure 4A, where Vd = Vs = Vsub = 0. The current detected at the S/D terminal corresponds to the electron component of gate current, denoted by Ie, while the current detected at the substrate corresponds to the hole component, denoted by Ih. When Vg is larger than the threshold voltage, Ie corresponds to the tunneling current of inversion electrons from the Si substrate to the gate, whereas Ih corresponds to the sum of the tunneling current of valance-band electrons in the Si substrate to the gate (Weinberg et al., 1985;Schuegraf et al., 1994b;Shanware et al., 1999) and the tunneling back current of holes from the gate to the Si substrate (Schuegraf et al., 1994a;Schuegraf et al., 1994b;Kobayashi et al., 1995), as illustrated in Figure 4B.
The results of the carrier separation measurements are shown in Figures 4C and 4D for the HfO2 nonferro-FET and HZO FeFET, respectively. In these measurements, Vg of pristine samples was scanned from 0 V to the positive voltage where breakdown occurs. It can be seen that tunneling of inversion electrons is the main contribution of Ig for both the nonferro-FETs and FeFET. Ih is found to be under detection limit in a low Vg regime, but it rapidly increases at Vg close to the breakdown voltage.  (Schuegraf et al., 1994a;Schuegraf et al., 1994b;Takayanagi et al., 2001).
Results of repeated measurements of Ie and Ih in a Vg scan range of -2 V to 4 V are shown in Figure 5. It is interesting that rapidly increasing Ih and Ie at Vg > 3.5 V in the FeFET, together with noisy signals before breakdown, are recovered during the Vg backward scan, resulting in repeatable Ih-Vg and Ie-Vg characteristics. These results imply that, although rapidly increasing Ih is an indication that breakdown is going to be triggered, the permanent degradation still does not occur yet in this condition and occurs when Ih increases in a step-wise manner, which can be observed in Figure 4D at Vg = 4.1 V.
The analysis above suggests that Ih is a convenient indicator for determining appropriate operating range of Vg. Figure 6 shows the I-Vg characteristics of the FeFET when Vg was kept below 3.5 V. In this Vg range, the ferroelectric hysteresis can still be achieved with a satisfactory memory window of 1.7 V while Ih is suppressed to under the detection limit. Note that Isub at negative Vg is due to gateinduced drain leakage (GIDL), which is unrelated to gate leakage currents. Although Ih does not necessarily imply to device degradation as discussed in Figure 5, hole tunneling back is flowing and leads to a higher probability that breakdown is triggered; therefore, the operating condition with high Ih should be avoided. The reliability of FeFETs operating in this way is notably improved and we cannot observe breakdown under electrical stress for a practically long time (> 10 5 s).

Time-dependent dielectric breakdown: Constant voltage stress and interrupted test
TDDB tests with a carrier separation setup were carried out to gain more insights into the breakdown behavior of FeFETs. Ie(t) and Ih(t) under constant voltage stress (CVS) as a function of stress time t are shown in Figures 7A and 7B for nonferro-FETs and FeFETs, respectively. Both Ie(t) and Ih(t) of the FeFET increase with time, which is in the opposite direction of Ie(t) of nonferro-FETs in the early stage. Note that Ih of nonferro-FETs is so low that cannot be measured until breakdown, indicating that there is less hole tunneling back in nonferro-FETs. We call the behavior of FeFETs having Ie(t) increasing with time as a SILC-like behavior, as stress-induced leakage current (SILC) refers to a phenomenon that a leakage current increases with electrical stress. This SILC-like behavior of Ie(t) of FeFETs can be fitted with a power-law function to be e ∝ I t , independent of Vg stress, as displayed in Figures 7C. Increasing gate current over time becomes positive feedback to the damage in the gate insulator, leading to breakdown when Ie is raised to the order of A/cm 2 . The Ie and Ih levels that trigger breakdown are almost independent of the stress voltage Vg. Figures 7D and 7E for nonferro-FETs and FeFETs, respectively. Not only the breakdown at lower Vg than nonferro-FETs but also tBD more sensitive to Vg can be observed for FeFETs, with tBD of approximately 10 3 s at Vg = 3.75 V reduced to approximately 10 -1 s at Vg = 4.2 V. The results of charge-to-breakdown QBD for electrons Qe = e ( ) ∫ I t dt and holes Qe = h ( ) ∫ I t dt are summarized in Figures 7F and 7G for non-ferro FETs and FeFETs, respectively. An obvious difference in the QBD-Vg properties in FeFETs and nonferro-FETs can be observed. While the total electron fluence Qe of nonferro-FETs at which the breakdown of HfO2 gate insulators occurs has only a weak dependence on stress voltage (note that Qh could not be extracted as Ih was too low), the total electron Qe and hole fluences Qh at which FeFETs reach breakdown vary in a wide range, implying that the total fluence is not a factor that is responsible for the trigger of breakdown of HZO insulators in FeFETs. Figure 7H shows the ratio of Qe/Qh at different stress voltages. It is interesting that the electron-to-hole ratio of QBD of FeFETs is almost constant independent of stress voltage. This behavior is remarkably different from conventional SiO2-gate MOSFETs, where the hole fluence Qh triggers gate dielectric breakdown and the Qe/Qh ratio is not a constant (Chen et al., 1986;Schuegraf et al., 1994a). This finding indicates that the gate dielectric breakdown mechanism in FeFETs should be different from SiO2-gate MOSFETs. We could not compare with nonferro-FETs as Qh was below the detection limit, so further investigation of the Qe/Qh ratio in nonferro-FETs is needed to specify whether or not the constant Qe/Qh ratio is a unique feature of FeFETs. Further studies of what physical parameters trigger the breakdown of HZO insulators in FeFETs would provide a clearer understanding of the interaction between the leakage current and gate dielectric breakdown event in FeFETs.

Time-to-breakdown tBD under CVS are summarized in
We have observed from Figure 7B that gate leakage increases with stress time, as similar to a SILClike behavior. Here, we investigate the device behavior during the increase of gate leakage current. Figures 8A and 8C show the I-Vg characteristics before and after a CVS at 4 V for 10 s shown in Figure 8B. Although Ie(t) and Ih(t) increase by approximately 100 times during the 10-s CVS test, it is found that an only small change of the I-Vg characteristics can be observed after stress. This implies that increases of Ie(t) and Ih(t) in FeFETs are not similar to typical SILC, where increasing current cannot be easily recovered: increasing currents in FeFETs can be recovered after releasing the stress.
This peculiar behavior of the gate leakage current is further investigated by applying interrupt pulses during TDDB tests. Figure 9A displays a voltage waveform when TDDB tests stressed at Vg = 4 V were interrupted by Vg = 0 V for 1 s every stress time of ts. Figures 9B,C show Ie(t) and Ih(t) for each stress cycle when ts = 10 s (cycles of 4 V for 10 s and 0 V for 1 s). Ie(t) and Ih(t) increase cycle by cycle regardless of interrupts by 0 V, implying that electrical stress keeps accumulated. Figure 9D summarizes the time-to-breakdown tBD (excluding interrupt time at 0 V). tBD independent of interrupt frequency indicates that the interrupts at 0 V have no significant effect on tBD. On the other hand, interrupting with negative voltage of Vg = -4 V is different. Figure 9E displays a voltage waveform when interrupted by Vg = -4 V for 1 s every stress time ts. Figures 9F,G illustrate that the SILC-like gate leakage current is recovered after interrupted with Vg = -4 V for 1 s: increasing Ie(t) and Ih(t) are recovered back almost to Ie(t = 0) and Ih(t = 0), respectively, in every cycle. Note that only the current at the first cycle was slightly different because the polarization state of pristine devices is different. This is in agreement with the repeatable Ig-Vg and Isub-Vg in Figure 5. Due to the recovery of SILC-like behavior, applying negative voltage interruption in this way helps extend the time-tobreakdown tBD by more than an order of magnitude, as summarized in Figure 9H.

Mechanism under voltage stress
The behavior of stress recovery by negative interrupt pulses can be found as well in HfO2 nonferro-FETs, as shown in Figures 10A,B. These facts suggest that although the leakage current and breakdown voltage of HfO2 nonferro-FETs and HZO FeFETs are different in detail due to differences in crystallinity or defect density, the fundamental mechanisms of the breakdown and recovery behavior should be generally similar in HfO2-based materials, for instance, same type of defect generation.
Considering the above findings, we propose the mechanism under high Vg stress, shown in Figure 11. Typically, SILC as well as noisy gate leakage current (PBD; progressive breakdown) under electrical stress before hard breakdown are attributed to the generation of defects such as oxygen vacancies (Olivo et al., 1988;Rofan et al., 1991;DiMaria et al., 1995;Degraeve et al, 1995). On the other hand, the recovery and repeatable behavior of apparently degraded gate leakage currents observed in FeFETs suggests that the defect redistribution should be the main contribution of apparently degraded characteristics rather than the generation of new defects. These defects are redistributed again after applying an opposite voltage pulse, recovered to the condition close to the initial one before stress. This model is supported by the fact that oxygen vacancies can move during the voltage cycling (Pešić et al., 2016;Florent et al., 2018b). However, if the stress is large enough for defects to move to the condition that triggers hard breakdown, suddenly increasing current generates a huge density of defects, which forms a permanent conduction path and results in the failure of the device. Then, the recovery is no longer available for devices that reach the breakdown condition.
Such a memory operation that the polarization states are frequently switched in a bipolar manner can help extend the device lifetime in terms of breakdown failure. In other words, not only the improvement in the material aspect but also choosing an appropriate memory operation is important for the reliability of FeFETs. Whereas bipolar operation is favorable to improving the breakdownlimited endurance, the memory-window-limited endurance has been reported to have the opposite behavior: memory window narrowing is degraded in a bipolar operation faster than in a unipolar operation (Yurchuk et al, 2014). These findings address that the ideal writing operation on the aspects of breakdown and MW narrowing are different. Thus, the endurance tests for evaluating the real lifetime should be carefully designed. Conventional endurance tests of FeFETs using bipolar stress evaluates only one aspect of device endurance, resulting in underestimation of gate dielectric breakdown and overestimation of MW narrowing.

Conclusion
We investigated the behavior of stress-induced degradation and gate dielectric breakdown in FeFETs with ferroelectric HZO as gate dielectrics on Si substrates. It was observed that gate dielectric breakdown in FeFETs is dominated by the breakdown in the HZO layer, not in the IL. Increasing gate and substrate hole currents under stress, due to the defect movement in HZO, were observed before gate dielectric breakdown occurs. These increasing currents are not a permanent phenomenon: temporary degradation is recovered by applying opposite voltage because of defect redistribution. We found that continuous electrical stress with the same polarity leads to easier hard breakdown, whereas bipolar stress frequently recovers the device distribution and help extend the time-to-breakdown. Because bipolar stress suppresses the breakdown-limited endurance while accelerates the memory window-limited endurance, accurate endurance tests should be carried out to correctly evaluate the endurance characteristics of FeFETs in practical memory operations.          The SILC-like behavior is attributed to the redistribution of defects rather than permanent defect generation as recovery is observed. Too much stress will trigger breakdown.