On Local Activity and Edge of Chaos in a NaMLab Memristor

Local activity is the capability of a system to amplify infinitesimal fluctuations in energy. Complex phenomena, including the generation of action potentials in neuronal axon membranes, may never emerge in an open system unless some of its constitutive elements operate in a locally active regime. As a result, the recent discovery of solid-state volatile memory devices, which, biased through appropriate DC sources, may enter a local activity domain, and, most importantly, the associated stable yet excitable sub-domain, referred to as edge of chaos, which is where the seed of complexity is actually planted, is of great appeal to the neuromorphic engineering community. This paper applies fundamentals from the theory of local activity to an accurate model of a niobium oxide volatile resistance switching memory to derive the conditions necessary to bias the device in the local activity regime. This allows to partition the entire design parameter space into three domains, where the threshold switch is locally passive (LP), locally active but unstable, and both locally active and stable, respectively. The final part of the article is devoted to point out the extent by which the response of the volatile memristor to quasi-static excitations may differ from its dynamics under DC stress. Reporting experimental measurements, which validate the theoretical predictions, this work clearly demonstrates how invaluable is non-linear system theory for the acquirement of a comprehensive picture of the dynamics of highly non-linear devices, which is an essential prerequisite for a conscious and systematic approach to the design of robust neuromorphic electronics. Given that, as recently proved, the potassium and sodium ion channels in biological axon membranes are locally active memristors, the physical realization of novel artificial neural networks, capable to reproduce the functionalities of the human brain more closely than state-of-the-art purely CMOS hardware architectures, should not leave aside the adoption of resistance switching memories, which, under the appropriate provision of energy, are capable to amplify the small signal, such as the niobium dioxide micro-scale device from NaMLab, chosen as object of theoretical and experimental study in this work.

Local activity is the capability of a system to amplify infinitesimal fluctuations in energy. Complex phenomena, including the generation of action potentials in neuronal axon membranes, may never emerge in an open system unless some of its constitutive elements operate in a locally active regime. As a result, the recent discovery of solid-state volatile memory devices, which, biased through appropriate DC sources, may enter a local activity domain, and, most importantly, the associated stable yet excitable subdomain, referred to as edge of chaos, which is where the seed of complexity is actually planted, is of great appeal to the neuromorphic engineering community. This paper applies fundamentals from the theory of local activity to an accurate model of a niobium oxide volatile resistance switching memory to derive the conditions necessary to bias the device in the local activity regime. This allows to partition the entire design parameter space into three domains, where the threshold switch is locally passive (LP), locally active but unstable, and both locally active and stable, respectively. The final part of the article is devoted to point out the extent by which the response of the volatile memristor to quasistatic excitations may differ from its dynamics under DC stress. Reporting experimental measurements, which validate the theoretical predictions, this work clearly demonstrates how invaluable is non-linear system theory for the acquirement of a comprehensive picture of the dynamics of highly non-linear devices, which is an essential prerequisite for a conscious and systematic approach to the design of robust neuromorphic electronics. Given that, as recently proved, the potassium and sodium ion channels in biological axon membranes are locally active memristors, the physical realization of novel artificial neural networks, capable to reproduce the functionalities of the human brain more closely than state-of-the-art purely CMOS hardware architectures, should not leave aside the adoption of resistance switching memories, which, under the appropriate provision of energy, are capable to amplify the small signal, such as the niobium dioxide micro-scale device from NaMLab, chosen as object of theoretical and experimental study in this work.

INTRODUCTION
In recent years, both industry and academia have been devoting efforts toward the exploration of new materials for the fabrication of novel devices, which, combining a number of functionalities within a limited physical volume, may allow the circuit implementation of disruptive computing strategies, allowing to keep the integrated circuit performance (IC) trend predicted by Moore (1965) in the years to come, despite scientists/companies attempting to reduce CMOS transistor dimensions further shall inevitably face a progressive technological/economical failure (Global Foundries Ltd., 2018). In this regard, one of the nanotechnologies with the greatest potential for future electronics (Williams, 2017;Zidan et al., 2018) allows the realization of disruptive circuit elements, known as memoryresistors, or memristors for short (Chua, 1971(Chua, , 2014(Chua, , 2015Chua and Kang, 1976). While the most economically profitable application field of these two-terminal devices is the non-volatile memory sector (Mikolajick et al., 2009;Ielmini and Waser, 2016), their inherently rich dynamical behavior allows to use them alternatively for sensing or processing data. Their peculiar capability to merge a number of different functionalities locally makes them the key nanotechnology enabler toward the future hardware implementation of novel ground-breaking information processing paradigms, including in-memory-computing (Ielmini and Wong, 2018), bio-inspired mem-computing (Di Ventra and Traversa, 2018;Xia and Yang, 2019;Ascoli et al., 2020bAscoli et al., ,c, 2021Tetzlaff et al., 2020), and bio-sensing (Tzouvadaki et al., 2016(Tzouvadaki et al., , 2020 strategies. Moreover, the use of appropriate materials in their fabrication allows to adopt them as basic building blocks of biomimetic neuromorphic circuits (Burr et al., 2015;Yi et al., 2018;Bohaichuk et al., 2019;Fuller et al., 2019;Serb et al., 2020). In this respect, given that the memory and learning capabilities of biological synapses may be rather accurately captured by nonvolatile memristor models (Chua, 2013), and that potassium and sodium ion channels in biological axon membranes essentially are volatile memristors (Ascoli et al., 2020a), as formulated in 1952 from Hodgkin and Huxley in a seminal paper (Hodgkin and Huxley, 1952), for which they were awarded the Nobel Prize in Physiology in 1961, and theoretically proved out in 2012 from Chua in a milestone manuscript (Chua et al., 2012), explaining several paradoxes that arose from their erroneous identification as time-varying resistances, we may conclude that resistance switching memories shall definitely play a fundamental role in the development of bio-realistic hardware implementations of the human brain in the incoming years.
Scientists have already highlighted the capability of certain memristor physical realizations, capable to retain the information stored in their states under zero input, and featuring a finely tunable resistance, to mimic accurately the biological functionalities of synapses (Indiveri et al., 2013). Most importantly, in relation to the research work presented in this paper, other real-world memristors, which fail to store data under no power, but operate excellently as selector devices in non-volatile crossbar memory arrays, allowing to address sneakpath current issues (Zidan et al., 2013), share with the potassium and sodium ion channels the capability to amplify infinitesimal fluctuations in energy, a fundamental property also referred to as local activity (LA) (Mainzer and Chua, 2013), making them ideal candidates to build reliable electronic implementations of spiking neurons.
In order to study the complex dynamics, which volatile memristors, blessed with the capability to enter the locally active regime, and, most importantly, its sub-regime, known as edge of chaos (EOC) (Mainzer and Chua, 2013), where the seed of complexity is actually planted, may induce in circuits, which accommodate them, recurring to the foundations of the LA theory 1 (Chua, 2005) is absolutely necessary 2 . In this regard, the present manuscript employs concepts from the theory of complexity (Mainzer and Chua, 2013) as well as non-linear circuit-centered (Chua, 1987) and system Corinto et al., 2020) theory-centered methods to analyze an experimentally validated simple yet accurate model of a micro-scale volatile memristor 3 from NaMLab gGmbH (Mähne et al., 2013;Wylezich et al., 2014), allowing us to explain how to stabilize an operating point lying on the negative differential resistance (NDR) region of the device DC current-voltage characteristic, and to draw a comprehensive picture of the possible operating modes of the microstructure. It is instructive to observe that gaining a complete understanding of the non-linear dynamics of particular miniaturized resistance switching memories, which are capable to amplify the small signal superimposed on top of an appropriate bias level, e.g., those realized by Hewlett Packard (Pickett and Williams, 2012) or the ones manufactured at the NaMLab facilities and investigated in this manuscript, is a fundamental pre-requirement toward the future development of a systematic and conscious approach to design bio-inspired spiking neural networks, which, employing memristive electronic implementations of biological neurons , are expected to reproduce the extraordinarily rich panorama of computing functionalities of the human brain  beyond the current capabilities of traditional purely CMOS hardware (Chicca et al., 2014).
This article holds a strong pedagogical role, providing a legacy of theoretical knowledge to the next generation of scientists interested in the design of neuromorphic electronics. To the best of our knowledge, this is the very first time that the application of circuit and system-theoretic methods, supported by experimental validation, allows to draw a complete classification of all the admissible operating domains of a memristor, namely the LP, the LA, and the EOC regimes, under both voltage and current control. Importantly, this work paves the way toward the development of a novel systematic neuromorphic hardware design approach, in which variability-tolerant measures may be consciously taken to prevent its basic components from exiting safe operating modes.
In regard to the structure of the article, section 2 explores the DC behavior of the voltage-controlled volatile memristor from NaMLab, identifying the conditions that allow to bias the micro-scale device along the NDR region of its DC characteristic, where it is said to operate in the locally active regime. Section 3 introduces a rigorous discussion on the device LA, namely its capability to amplify infinitesimal fluctuations in energy, on the basis of the analysis of its small-signal equivalent circuit model, identifying also the conditions under which the NbO memristor may enter the "pearl" (Chua, 2005) embedded in the LA domain, namely the EOC, and, providing, finally, a complete classification of all the possible operating regimes of the threshold switch. Importantly, on the basis of concordant experimental measurements and model predictions, section 4 clarifies once and for all when and how does the response of the threshold switch to quasi-static stimuli differs from its DC behavior. A brief discussion, pinpointing the significance of this research work for the future development of a systematic method to design artificial neural networks capable to operate according to the same mem-computing principles lying at the basis of the human brain information processing paradigm, is provided in section 5. Conclusions are finally drafted in section 6. An Appendix with supplementary information on the microstructure under our magnifying glass in this work is provided in section 6.

EXPLORATION OF LA AND EOC IN AN NBO VOLATILE MEMRISTOR
The next section introduces a purely mathematical yet accurate model of a micro-scale niobium oxide (NbO) volatile memristor manufactured at NaMLab gGmbH (Mähne et al., 2013;Wylezich et al., 2014). Under the time invariance assumption 4 , each twoterminal circuit element from the class of voltage-controlled extended memristors is defined via the following differential algebraic equation (DAE) set 5 (Chua, 2018): where v m (i m ) stands for the voltage (current) falling across (flowing through) the one-port 6 , x [x 1 , x 2 , . . . , x k ] T ∈ R k denotes in general a k-dimensional memory state 7 , while both state evolution function g(·, ·) : R k × R → R k and memductance function G(·, ·) : R k × R → R depend upon state and input 4 A circuit element is said to be time invariant if its input-output behavior does not change over time. 5 The model of a current-controlled extended memristor may be derived mutatis mutandis from Equations (1) and (2) by invoking the duality principle (Chua, 1987). 6 The memristor voltage v m (current i m ) is also referred to as the input or control (output) variable of a voltage-controlled memristor. By the duality principle (Chua, 1987), a similar nomenclature may be adopted mutatis mutandis for a current-controlled memristor. 7 The memory state vector x of a volatile memristor is unable to store information, not even in digital binary form, for zero input. Therefore, precisely, it should be interpreted as a volatile memory state.
variables. Importantly, the inequality G(x, 0) = ∞ must hold true, i.e., the memductance function has to be finite for zero voltage in order for the model of an extended memristor to capture its coincident zero-crossing signature, which establishes that the output of the device always crosses the time axis at the same instants as its input 8 .
In case the memductance function is independent of the voltage stimulus, the DAE set (1) and (2) reduces to and the one-port is said to belong to the class of voltage-controlled generic memristors. Figure 1 illustrates the steps necessary to derive the DC current-voltage locus of a first-order voltage-controlled extended memristor 9 (Chua, 2014) systematically. It is worth to pinpoint that, actually, this rigorous procedure is never carried out in the lab. In fact, among experimentalists, it is common practice to perform quasi-DC tests (Chua, 2015), also referred to as quasistatic measurements, to characterize the DC current (voltage) response of a voltage (current)-controlled memristor. However, as will be clarified in section 4, extra care should be taken in the selection of the kind of excitation stimulus, i.e., a voltage or a current source, to use for the quasi-static test on a device sample in order to measure a close approximation to its DC characteristic.

Application of a Non-linear System Identification Technique for Modeling a NbO Volatile Memristor
The Unfolding Theorem 10 (Chua, 2011) defines a non-linear system identification method, which allows to determine a purely mathematical description of a memristor device in the voltage-current domain on the basis of a set of experimental data, without requiring a preliminary understanding of the physical mechanisms underlying the device operating principles. Applying this theorem, under low current operation 11 the 8 If the constraint G(x, 0) = ∞ were not included in the definition of an extended memristor, the DAE set (1) and (2) could be used to model other dynamic circuit elements, e.g., linear capacitors and inductors (Chua, 2014). 9 Invoking the duality principle (Chua, 1987) a similar recipe may be written down mutatis mutandis for the determination of the DC voltage-current characteristic of a first-order current-controlled extended memristor. 10 Referring to a first-order voltage-controlled extended memristor, the Unfolding Theorem (Chua, 2011) envisages the expansion of the state evolution function g(x, v m ) in Equation (1) and of the memductance function G(x, v m ) in Equation (2), for x = x, into sums and products of polynomial series in input and state variables. 11 Keeping the maximum current flowing through the device below an upper bound of about 15 mA, the threshold switching dynamics emerging in the NbO micro-film are not found to be accompanied by non-volatile memory effects. However, if higher currents are let flow through the device, the latter is found to feature distinct resistive levels for no input (Mähne et al., 2013) besides maintaining an abrupt switching behavior upon excitation. For modeling the NbO memristor accurately under these circumstances, the dynamic law of another non-volatile memory state needs to be specified (Slesazeck et al., 2016). Since the device was operated in the low current regime during all the experimental investigations associated to this research, a volatile memristor model is adopted non-linear dynamics of a micro-scale NbO volatile resistance switching memory from NaMlab was found to be captured accurately by a voltage-controlled generic memristor model, reading as the DAE set (3) and (4), where the state evolution and memductance functions are respectively, expressed by in which the coefficient values, tuned through a standard optimization procedure, are reported in Table 1.

DRM-and Circuit-Theoretic Based Investigations of the Device DC Response
Following the iterative procedure given in Figure 1, the voltage V s of a hypothetical DC source, inserted in parallel to the NbO device, is varied in small steps from 0 V to 1.046 V, and, for each value of the voltage V m = V s , which consequently falls across the memristor 12 , the following operations are executed.
• All the possible zeros X I , X II , . . ., and X n of the associated state evolution function g(x, V s ) in Equation (5) are first calculated.
in this manuscript to capture the dynamics of the NbO threshold switch. However, for pedagogical reasons, and for the sake of completeness, some of the theoretical results, descending from the analysis of this model, e.g., the device DC currentvoltage characteristic, shall cover also the high current regime. 12 V m , X, and I m denote the DC values for memristor voltage, state, and current, respectively. The triplet (V m , X, I m ) defines a DC operating point for the memristor.  (5) and memductance function (6) in the proposed NbO micro-device model (3) and (4).
5.19 · 10 9 −2.05 · 10 7 7.21 · 10 9 −0.07 · 10 9 2.27 · 10 5 c 23 c 24 c 25 d 0 d 1 −2.40 · 10 2 1.25 · 10 −1 −2.69 · 10 −5 6.50 · 10 −3 −6.66 · 10 −5 d 2 d 3 d 4 2.14 · 10 −7 −2.14 · 10 −10 1.19 · 10 −13 A voltage-controlled memristor DAE set (1) and (2), adapted to the first-order case, and with g(x, vm) and G(x, vm) expressed as sums and products of polynomial series in input and state variables, was chosen as model template. Adopting a bottom-up approach, a standard optimization procedure was set in place to massage the coefficients of the simplest possible form of the polynomial-based model template so as to decrease the cumulative Relative Root Mean Quadratic Error (RRMQE) between a multivariate set of experimental data extracted from a device sample and the corresponding model predictions below a predefined threshold. The complexity of the two series expansions was progressively increased after ensuring that any possible simpler model would fail to meet the objective of the optimization procedure. As compared to the parameter setting, tabulated in Ascoli et al. (2015), where the proposed model was originally formulated, an additional fine tuning of the real coefficients in the polynomial series expansions of g(x, vm) and G(x, vm) was carried out so as to fit the DAE set to experimental data extracted from a different NbO micro-scale device sample.
• The n memory state DC values are then inserted into Ohm's law (4) to obtain the associated currents I m,I = G(X I ) · V s , I m,II = G(X II ) · V s , . . ., and I m,n = G(X n ) · V s , where the memductance function is expressed by Equation (6). Interpolating all the points, obtained through the entire cycle of iterations, delivers, finally, the DC characteristic of the microscale device. Figure 2A shows all the possible DC operating points of the memristor state, i.e., all the X-values, at which the state equation (3), with state evolution function (5), vanishes, for each V m value. Correspondingly, using Ohm's law (4), with memductance function (6), the locus of the memory state DC operating point X vs. the device DC current I m is found to be illustrated by Figure 2B. Importantly, X is a multi ( Figure 1, applicable to current-controlled extended memristors, to the current-driven version of the proposed NbO device model DAE set (3) and (4) with g(x, v m ) and G(x) expressed by Equations (5) and (6), respectively, i.e., to the current-controlled generic memristor DAE set where f(·, ·) : R n ×R → R n , denoting the state evolution function, and R(·) : R n → R, standing for the memristance function, are respectively, expressed as and sweeping the memristor DC current I m within the range 15 [I m,a , I m,b ] = [0, 500 mA].
Calculating the slope of the DC current-voltage locus at each point, which lies along it, the small-signal or differential or local 13 Setting to 0 the state evolution function (5) for V m = V m,a = 0 V, the formula for the unique memristor state equilibrium is easily found to be X a = X(V m,a ) = X(V m = 0 V) = −a 0 /a 1 = 253.15. 14 In this article, the abscissa and ordinate of a generic operating point Q m,ii ∈ {I, II, . . .}-along the device DC I m -V m characteristic are denoted as V m,i and I m,i , respectively. 15 This approach is simpler than the one assuming a voltage control, since, here, the "dual" recipe of the procedure illustrated in Figure 1, applicable to any currentdriven extended memristor model, would require the numerical calculation of a single zero for the state evolution function (9) for each DC value I m assigned to the memristor current i m (as may be inferred from Figure 2B, X is a singlevalued function of I m ). Importantly, under current sweep, each memristor state DC operating point X is found to be globally asymptotically stable, as will be discussed in more depth shortly (see Figure 2B for more details). As a result, according to the color coding convention adopted in Figure 2, all the points in the loci from plots (A-C) should be marked in blue under current control.
The range of X-values (X 1 , X 2 ) = (351, 1, 006), where r < 0 , defines the negative differential resistance (NDR) region of the DC I m -V m characteristic of the micro-scale threshold switch ( Figure 3B). The range of X-values [X a , X 1 ) = [253, 351) ((X 2 , X b = [1, 006, 1, 722]), where r > 0 , defines the lower (upper) positive differential resistance (PDR) region of the DC I m -V m characteristic of the micro-scale threshold switch 16 . REMARK 2. The values of the memristor state in the proposed model reveal an association between x and the device internal temperature T. On the basis of this assumption, given that the memristor state X range along the NDR region, specifically (X 1 , X 2 ) = (351, 1, 006), indicates that the threshold switch does not attain the NbO Mott phase transition temperature of T Mott = 1, 050 K throughout the operating mode where it features a small-signal conductance of negative polarity. This conjecture, examined in Slesazeck et al. (2015), was recently adopted and confirmed in other prominent scientific studies (Gibson et al., 2016;Kumar et al., 2017).
A deeper understanding of the device non-linear behavior may be inferred by studying its dynamic route map (DRM) (Chua, 2018), a powerful graphical tool for the analysis of first-order dynamical systems 17 . Figure 4A depicts the NbO device state dynamic routes (SDRs) for each value of the memristor DC voltage V m in the set S V m {0, 0.625, 0.875, 1.04} V. As V m is progressively 16 In Figure 12, the lower (upper) PDR branch of the device DC I m -V m locus will be referred to as PDR region 1 (2). 17 Let a first-order dynamical system be described by a non-linear ODE of the formẋ = f (x, µ), where x ∈ R denotes the state variable, µ ∈ R stands for a control parameter, and f (·, ·) : R × R → R defines the state evolution function.
Plotting the time derivativeẋ of the state variable vs. the state variable itself for a specific valueμ of the control parameters µ, and endowing the resulting locus with arrows pointing toward the east (west) on the positive (negative) half plane, provides a state dynamic route (SDR), illustrating the path, which x follows from any initial condition x 0 x(0) in this scenario. An ODE equilibriumx for µ =μ corresponds to a state, which lies along the horizontal axis on the f (x,μ) vs. x locus (ẋ vanishes at its location), and is said to be asymptotically stable (to be unstable) if the SDR features a negative (positive) slope therein, implying that, perturbing the system slightly away from its position, the system solution moves back to (departs from) it as time proceeds. The dynamic route map (DRM) of the first-order system is a family of SDRs, one for each of the admissible values of the control parameter µ. Importantly, X is the symbol adopted in this article to denote a zero of the memristor state evolution function in Equations (5) and (9), namely g(x, v m ) (f (x, i m ) = g(x, R(x) · i m ), with R(x) = G −1 (x), as established by Equation (10), and G(x) expressed by formula (6)) under a given DC V m (I m ) value. X, referred to as an equilibrium for the memristor state Equations (3) and (7), with state evolution function expressed by formula (5) and (9), under the specified bias voltage (current) stimulus V m (I m ), indicates a possible DC operating point for the memristor state in this scenario. Finally, it is worth mentioning that, recently, the DRM graphical tool has been extended to nonlinear dynamical systems with two degrees of freedom (Tetzlaff et al., 2020), which shall allow, for example, an in-depth study of the nonlinear dynamics of second-order memristors. The pointsQ m,1 = (V m,1 , X 1 ) and Q m,2 = (V m,2 , X 2 ), respectively located at the lower and upper bound of the NDR region in the V m -X plane, are shown in (A). The corresponding pair of points in the I m -X (V m -I m ) plane, namelyQ m,1 = (I m,1 , X 1 ) andQ m,2 = (I m,2 , X 2 ) (Q m,1 = (V m,1 , I m,1 ) and Q m,2 = (V m,2 , I m,2 )), are shown in (B,C).

FIGURE 3 | (A)
Small-signal resistance r | x=X of the NbO memristor vs. memory state DC operating point X. In red (blue), the NDR (PDR) values, which, as revealed in the text, are associated to unstable (stable) memory state DC operating points for the voltage-driven memristor device. (B) Close-up view on the NDR region, identifiable on the horizontal axis for each X-value within the range [351,1006]. Note thatr, defined in Equation (16), and denoting the largest modulus of the device small-signal resistance in the NDR region, appears at X = 411, and is equal to 21.43 . Another state bias point of significance for the remainder of this manuscript is X = 478, where r is found to be equal to −16.514 .
increased within this set, for the first zero input scenario the voltage-driven memristor exhibits a globally asymptotically stable state operating point. The locus ofẋ vs. x under no input, known as power-off plot (POP) (Chua, 2015) and depicted in pink in plot (A), crosses in fact the state axis in a single point, namely X = − a 0 a 1 = 253.15, with negative slope, confirming that, as anticipated earlier, the micro-scale device from NaMLab is a volatile memory under the relatively low current range under focus. The blue SDR, resulting upon the assignment of the second DC value in the set S V m to V m , also crosses once and with negative slope the state axis, specifically in X = 267, and, correspondingly, the memristor keeps its monostable character in this case. As the DC input is further increased, the memristive system loses monostability, acquiring the capability to evolve toward one of two possible operating points. For V m = 0.875 V, the SDR, drawn in red in plot (A), crosses the memory state axis in three points, specifically X l = 289, X = 612, and X r = 1, 456, of which each of the outer ones (of which the center one) are locally stable (is unstable), given that dẋ dx V m =0.875 V is negative (positive) therein. Increasing the DC input further, the device undergoes a reverse bifurcation from bistability back to monostability. For the last V m -value in S V m , the SDR, illustrated in brown in plot (A), admits once again a negative slope in the single location, where it crosses the horizontal axis, namely in X = 1, 725, and, as a result, the memristor exhibits one and only one globally asymptotically stable operating point.
Thus, the memristor SDR, resulting upon assigning the first, second, and fourth values (the third value) in  Figure 2C, the device exhibits a monostable character, except for V m ∈ [0.826, 1.007V], where it is found to feature bistability. On the other hand, for each DC current I m value in the range [0, 500 mA] from Figure 2C, the memristor keeps monostability. In both plots a hollow (filled) circle on the horizontal axis indicates an unstable (a stable) memristor state DC operating point X under a given DC input. The pink-colored POP of the device under either voltage or current control crosses the state axis with negative slope at X = − a0 a1 = 253.15, clearly classifying the NbO memristor as a volatile memory according to the proposed model. Also for V m = 0.625 V, or, alternatively, for I m = 0.31 mA (for V m = 1.04 V, or, alternatively, for I m = 492 mA), the blue (brown) SDR under voltage, or, alternatively, current control, admits a single intersection with the state axis, namely X = 267 (X = 1725), and negative slope therein. For V m = 0.875 V, the device features three possible equilibria, namely X l = 289, X = 612, and X r = 1456, of which only the outer ones are stable, as may be inferred from (A). The memristor may asymptotically attain the first, second, and third operating point in this triplet by letting a specific DC current, equal to 0.68, 11.80, and 207 mA, respectively, flow through the device, as revealed by the red SDR in solid, dashed, and dash-dotted line style in (B).
the set S V m to the device DC voltage V m , admits the first, second, and sixth value (the third, fourth, and fifth values) for the memristor state operating point X in the set S X ∈ {253, 267, 289, 612, 1, 456, 1, 725}. From Ohm's law-refer to Equations (4)-(6)-or using directly the data associated with the device DC current-voltage locus in Figure 2C, it may be evinced that the memristor may attain the kth equilibrium in the set S X also upon letting a DC current of value equal to the k th number in the set S I m {0, 0.31, 0.68, 11.80, 207, 492} mA flow across the device (k ∈ {1, 2, 3, 4, 5, 6}). Figure 4B depicts the locus of the state evolution function (5), with memristor voltage expressed as v m = G −1 (x) · i m , for each DC value i m = I m in S I m . With reference to Figure 4, the SDR (all the SDRs), appearing in plot (B), and, respectively, associated with the first, second, and sixth value (respectively, associated with the third, fourth, and fifth values) of the memristor DC current I m in S I m is in turn drawn in pink, blue, and brown (are drawn in red), as the SDR, which admits the same equilibrium (admits each of their three distinct equilibria) under voltage control, i.e., the one shown in plot (A), and obtained upon assigning the first, second, and fourth (assigning the third) value in the set S V m to the memristor DC voltage V m . Remarkably, each of the memristor SDRs, corresponding to values of the device DC current I m in the set S I m , admits one and only one intersection with the horizontal axis, crossing it with a negative slope, which demonstrates the robust nature of the monostability of the device under current control. REMARK 3. A deeper understanding may be gained by analyzing the memristor DC response from a circuit-theoretic perspective. The load line corresponding to the scenario, where a voltage (current) source V s (I s ) is applied directly across the NbO threshold switch, corresponds to a vertical (horizontal) linear locus of ) between the vertical (horizontal) load line and the memristor DC I m -V m characteristic is a possible operating point for the device. With reference to Figure 5, for each V s value in the set {0, 0.625} V (for V s = 1.04 V) the memristor admits a unique operating point Q m , with coordinates reported in plots (A) and (C), and with a globally asymptotically stable character, as clear from the analysis of the respective SDR in Figure 4A. For example, stressing the device with a DC voltage of value V s = 0.625 V, as shown through a red color in Figure 6A, the threshold switch may be polarized in one and only one globally asymptotically stable operating point, which lies on the lower PDR of its DC I m -V m characteristic, specifically at Q m = (V m , I m ) = (0.625 V, 0.31 mA), as expected from Figure 5A, and demonstrated through a numerical simulation of the proposed polynomial-based model (see Figures 6A,B, depicting in blue the time evolution of memristor current and state, respectively).
However, as illustrated in Figure 5B, for V s = 0.875 V, three are the voltage-current pairs, at which the device DC characteristic crosses the respective vertical load line, i.e., Q m,l , Q m , and Q m,r , of which the one (the two) lying on (outside of) the NDR region of the DC I m -V m locus is unstable (are locally asymptotically stable), as established through the investigation of the respective SDR in Figure 4A. Stimulating the NbO threshold switch by means of a source of DC voltage V s = 0.875 V, as shown in red in Figure 6C, a couple of numerical simulations of the proposed unfolding theorem-based model provide evidence for the threshold switch bistability. Setting the initial memristor state x 0 below (above) the unstable point X = 612, the device may be polarized in a locally asymptotically stable operating point lying on the lower (upper) PDR branch of its DC I m -V m characteristic, in particular at Q m,l = (0.875 V, 0.68 mA) [Q m,r = (0.875 V, 207 mA)], as expected from Figure 5B, and illustrated in Figures 6C,D, depicting in blue and with a dash-dotted (solid) linestyle the approach of memristor current and state to the lower (upper) bias solution from the admissible stable pair, respectively.
On the contrary, referring once more to Figure 5, for each I s value in S I m -see plots (A), (B), and (C) for I s ∈ {0, 0.31} mA, for I s ∈ {0.68, 11.80, 207, } mA, and for I s = 462 mA, respectivelythe device is found to possess one and only one operating point Q m , which is globally asymptotically stable, as determined earlier on through the study of the respective current-driven memristor SDRs shown in Figure 4B. Applying a source of DC current I s = 11.80 mA directly across the threshold switch, as shown in red in Figure 7A, a numerical simulation of the polynomial-based model demonstrates the global asymptotic stability of the operating point Q m = (V m , I m ) = (0.875 V, 11.80 mA), lying on the NDR branch of the device DC characteristic. Setting the initial condition x 0 arbitrarily to 253.15, the device is indeed found to converge asymptotically toward this NDR bias point, as expected from Figure 5B, and visualized in Figures 7A,B, where the memristor voltage (state) is found to approach the value V m = 0.875 V (X = 612) as time goes to ∞.

NDR Stabilization Under Voltage Control
The analysis of section 2.2 has revealed that the memristor may be biased in any point of the NDR region of its DC I m -V m locus by letting a suitable DC current flow through it. On the other hand, the entire NDR region of the memristor DC current-voltage characteristic is unstable under voltage control. This notwithstanding, it is possible to stabilize any point along the NDR domain by inserting a linear resistor R s of appropriate resistance between the DC voltage source V s and the memristor, as shown in Figure 8A. This section explains how to tune the parameters of the biasing circuit in this figure for the stabilization of a given NDR operating point Q m = (V m , I m ) on the memristor DC I m -V m characteristic 18 . An example shall be used to illustrate this concept. Suppose it is desirable to stabilize the memristor state equilibrium X = 478, i.e., equivalently, the corresponding operating point Q m = (0.937 V, 5.948 mA) on the device DC characteristic. Let us select the parameters V s and R s of the biasing circuit in three distinct ways, and analyze the resulting scenarios. First, applying a DC voltage of value V s = 0.937 V directly across the threshold switch, i.e., without introducing a series resistor in Figure 8A, the respective voltage-controlled memristor SDR, depicted in black in Figure 9A, and obtained by plotting the state evolution function of Equation (5) with v m = V s against the state x, admits a triplet of intersections with the horizontal axis, namely X l = 301, X = 478, and X r = 1, 601, of which the intermediate one is unstable. Let us now insert a series resistance of value R s = 10.59 between a DC voltage source of value V s = 1 V and the memristor. Also in this second scenario the memristor exhibits three possible equilibria, specifically X l = 319, X = 478, and X r = 613, of which the center one is still unstable, as revealed by the positive slope 18 Note that a unique memristor state X is associated to each point Q m = (V m , I m ) along the DC I m -V m characteristic, as clear from Figure 2. featured therein by the resulting voltage-controlled memristor SDR, drawn in red in Figure 9A, and derived by expressing the memristor voltage v m -refer to the circuit in Figure 8A Finally, let us now increase the resistance R s of the series resistance up to 330 , and set the value V s of the DC voltage source to 2.9 V. The SDR, which the voltage-driven threshold switch features in this scenario, is illustrated in blue in Figure 9A.
Remarkably, the locus of the time derivative of the state vs. the state itself in this occasion crosses the horizontal axis only once in the location X = 478 with a negative slope. Thus, in this third scenario, the parameter setting of the biasing circuit of Figure Figure 8A for R s = 0 is mathematically described by 19 For (V s , R s ) = (1 V, 10.59 ), referring to the second scenario, the load line, depicted in red in Figure 9B, also crosses the device DC I m -V m locus in three points, namely Q m,l = (0.986 V, 1.294 mA), Q m = (0.937 V, 5.948 mA), and Q m,r = (0.875 V, 11.82 mA), of which the center one is associated to the unstable state equilibrium X = 478, as follows from the investigation of the red-colored voltage-controlled memristor SDR in Figure 9A. With reference to Figure 9, in the third scenario, where (V s , R s ) = (2.9 V, 330 ), the load line, depicted in blue in plot (B), crosses the device DC I m -V m locus in a single point, specifically the desired one, i.e., Q m = (0.937 V, 5.948 mA), which is associated to the globally asymptotically stable state equilibrium X = 478, as results from the study of the blue-colored voltage-controlled memristor SDR in plot (A).
REMARK 4. With reference to Figure 9, plot (C) offers a close-up view of plot (B) in the region surrounding the desired bias point  Figure 4A, the lower and upper operating points, marked via red filled circles (the middle operating point, marked via a red hollow circle), are locally stable (is unstable) under voltage control. Q m,l , Q m , and Q m,r may also be independently set by driving the NbO memristor with a DC current of value 0.68, 11.80, and 207 mA, respectively, as identified by the intersection of the device DC characteristic with the red horizontal load line in solid, dashed, and dash-dotted line style, respectively. As may be evinced by the red solid, dashed, and dashed-dotted SDRs in Figure  In fact, the stabilization of a DC operating point Q m along the NDR region of the memristor DC locus is guaranteed as long as where, as anticipated in section 2.2, r | Q m , the small-signal or differential or local resistance at Q m , is defined as FIGURE 6 | Response of the NbO threshold switch to the application of an independent source of DC voltage V s between its two terminals. (A) Memristor current (blue) under DC voltage stress with V s = 0.625 V (red). Here, the load line-refer to the vertical blue line in Figure 5A-intersects the memristor DC locus in the lower PDR branch. (B) Time waveform of the memristor state, converging to the globally asymptotically stable value X = 267 as t tends to ∞. (C) Dash-dotted (solid) blue waveform: Current through the NbO micro-structure under DC voltage stress with V s = 0.875 V (red) and for an initial condition x 0 smaller (larger) than the unstable memristor operating state X = 612, constituting the separatrix between the basins of attraction of the two-locally stable bias memory states X l = 289 and X r = 1456 (recall Figure 4). Here the load line-refer to the vertical red line in Figure 5B-crosses the memristor DC characteristic in the NDR region, where the unstable operating point lies, as well as in either of the two PDR regions, where the threshold switch may be found asymptotically. (D) Dash-dotted (solid) blue solution: Time evolution of the memristor state, converging to the locally asymptotically stable value X l = 289 (X r = 1, 456) as t tends to ∞, for x 0 < (>)X = 612.  Choosing the resistance of the series resistor such that denoting the largest modulus of the differential resistance across the NDR region of the device DC characteristic is sufficient to stabilize every operating point along it. With reference to Figure 3, for our NbO threshold switchr = 21.43 at X = 411, and the series resistor resistance adopted most frequently in this article, i.e., R s = 330 , is large enough to stabilize the entire NDR region of its DC I m -V m locus. Figure 10 demonstrates that, setting the biasing circuit parameters V s and R s in the circuit of Figure 8A to 2.9 V, and 330 , respectively, the memristor state, voltage, and current settle asymptotically to the desired values X = 478, V m = 0.937 V, and 5.948 mA, respectively.

LA AND EOC IN THE NBO VOLATILE MEMRISTOR
Before gaining a deep insight into the conditions under which the NbO threshold switch may enter the LA domain, and, most importantly, its "pearl"-subdomain, i.e., the EOC, let us define rigorously the fundamental concepts of LA and EOC.

LA and EOC: A Rigorous Definition
Without loss of generality, a first-order voltage-controlled 20 twoterminal memristor device with dynamic state x is considered here for introducing this fundamental notion. Let an opportune biasing circuit polarize the memristor in a certain point 20 Invoking the duality principle (Chua, 1987), similar conclusions apply mutatis mutandis to a first-order current-controlled two-terminal memristor. Furthermore, the local activity definition may be extended also to higher-order one-and multi-ports of memristive or non-memristive nature, as explained in Chua (1998).
Assume that an infinitesimal voltage signal δv m is superimposed on the memristor bias voltage V m at t = t 0 , generating a total voltage over the device equal to v m = V m + δv m thereafter. As a result, the device bias state X and current I m also drift by infinitesimal quantities, namely δx and δi m , respectively, leading to an overall state expressed by x = X + δx, and to a total current in the form i m = I m + δi m from the time instant of application of the local perturbation. The memristor is said to be locally active at Q m if and only if it is possible to identify at least one infinitesimal perturbation δv m = δv * m such that the small-signal or local net energy δE(t 0 ; t) absorbed by the device over the time interval [t 0 , t], and computed via by assuming the associated reference direction convention for memristor voltage and current 21 (Chua, 1987), is found to be negative for at least one finite time instant t = t * . This rigorous definition is however impractical for testing whether a memristor may ever enter the locally active regime, where it may amplify infinitesimal fluctuations in energy. In fact, before concluding that the device is LP across its entire DC current-voltage characteristic, one should ensure that the integral (17) keeps positive at all times and for each of the infinitely many infinitesimal perturbations, which may ever stimulate the memristor, and iterate this procedure for each of the infinitely many one-port bias points. However, and fortunately, there exists a theorem, known as LA Theorem (Chua, 2005), which provides necessary and sufficient conditions under which a oneport is locally active at a given operating point Q m . The theorem  Figure 8A with R s = 10.59 . Under these circumstances, the biasing circuit is unable to stabilize the state operating point X = 478, which, similarly as in the previous case, separates the basins of attractions of two locally stable state operating points, i.e., X l = 319 and X r = 613, located on its left and right, respectively. Blue curve: SDR of the memristor under the application of a DC voltage V s = 2.9 V across the series between a linear resistor of resistance R s = 330 and the memristor itself. In this scenario, the memristor features a single globally asymptotically stable state operating point, lying at the desired location X = 478. (B) DC current voltage-characteristic of the NbO device (green curve), load line corresponding to the scenario where a DC voltage source of value V s = 0.937 V is applied directly across the threshold switch (black vertical segment), load line in the case where a DC voltage source of value V s = 1 V is applied across the series combination between the memristor and a linear resistor with resistance R s = 10.59 (red negative-sloped segment), and load line for the circuit shown in Figure 8A with V s = 2.9 V and R s = 330 (blue negative-sloped segment). Only the stable operating points, appearing in each of the three scenarios, are highlighted, using filled circles, according to the convention adopted in this article.  (Chua, 1987), similar conclusions apply mutatis mutandis to a first-order current-controlled two-terminal memristor. Furthermore, the LA theorem may be generalized for the analysis of higher-order one-and multi-ports of memristive or non-memristive nature, as described in Chua (1998).  If and only if one and only one of the four conditions in this list, particularly the last one, holds true, the one-port is locally active around an asymptotically stable operating point Q m . In this case, the locally active one-port is said to be on the EOC, which has been dubbed the "pearl" of the LA domain in Chua (2005). If none of the four conditions listed above applies, the one-port is said to be LP at the given operating point.

Small-Signal Equivalent Circuit Model of the NbO Memristor
This section intends to derive the small-signal equivalent circuit model of the voltage-controlled threshold switch to allow the determination of its local admittance function Y m (s). Let us indicate with X the state operating point of the memristor under a DC voltage stimulus V m falling between its terminals, and with I m the resulting current flowing through the circuit element. With δx x − X denoting an infinitesimal change in the memristor state x with respect to its operating point X, resulting from the application of a small-signal perturbation δv m in addition to the DC bias voltage V m across its terminals, the linearization of state equation (3) and Ohm's law (4), with state evolution and memductance functions expressed by Equations (5) and (6), 26 The 3rd condition may never hold true for a first-order one-port. respectively, provides the following small-signal or local model for the NbO-based memristor: where δi m stands for a local variation in the memristor current with respect to the DC current I m due to the small-signal voltage input δv m , while the formulas for the local memristor model coefficients a, b, c, and d, respectively, are Frontiers in Neuroscience | www.frontiersin.org FIGURE 11 | Loci of the resistance R 1 (A), of the modulus of the resistance R 2 (B), and of the inductance L (C) in the small-signal equivalent circuit model of the NbO threshold switch from NaMLab as a function of the memristor state operating point X. In each plot, the red (blue) color is assigned to each branch corresponding to unstable (stable) state operating points under voltage control. As expected, given that it represents the instantaneous resistance R = G −1 of the threshold switch, which is a passive device, R 1 is positive at all operating points. R 2 is found to have a negative sign throughout the red-colored branch, i.e., along the whole NDR region of the memristor DC I m -V m characteristic (note, however, that R 1 + R 2 is found to be positive at all operating points). Finally, the sign of L is positive irrespective of X.
FIGURE 12 | Pole-zero diagram for the local admittance of the voltage-controlled NbO threshold switch from NaMLab GgmbH. While the zero is negative throughout the state operating domain X ∈ [X a , X b ] = [253, 1, 722] from Figure 2, the pole is negative (positive) in either of the two PDR regions X ∈ [X a , X 1 ) = [253, 351) and X ∈ (X 2 , X b ] = (1, 006, 1, 722] [throughout the NDR region X ∈ (X 1 , X 2 ) = (351, 1, 006)] of the threshold switch DC characteristic. Here s p1,Ym (s z1,Ym ) and s p2,Ym (s z2,Ym ), respectively, are the values of the pole (zero) of Y m (s) at the lower X 1 and upper X 2 bounds of the NDR state bias domain.
Taking the Laplace transform of each side in the local form of the state equation (18), with x(0) = 0, as well as of Ohm's law (19), we obtain: Solving Equation (24) for L{x(t)}, and inserting the resulting expression into Equation (25), the admittance-based transfer function Y m (s), defining, within the s-domain, the current response of the micro-scale device to a small-signal voltage stimulation around the operating point, is found to be expressed by Y m (s) represents the memristor small-signal or local or infinitesimal admittance. Its formula in Equation (26) may be implemented in circuit-theoretic form via the circuit, shown in Figure 8B, and consisting of the parallel combination between a linear resistor R 1 , and the series connection between yet another linear resistor R 2 and a linear inductor L. Of course, the values of the parameters of the electrical elements in this figure, showing essentially the small-signal equivalent circuit model of the NbO memristor, depend upon the memristor operating point under focus. From basic circuit-theoretic principles, the Laplace domain representation of the admittance of the one-port in Figure 8B is found to be expressed by Imposing the equivalence between the formula (27) for Y and the analytical expression (26) for Y m establishes the following constraints on the dependence of the parameters of the circuit of Figure 8B on the memristor bias point 27 : 27 Unless otherwise stated, in the remainder of the paper the memristor smallsignal admittance Y m will be expressed in terms of the parameters of the device small-signal equivalent circuit model of Figure 8B, i.e., through Equation (27). Figures 11A-C illustrate the resistance R 1 , the modulus of the resistance R 2 , and the inductance L as a function of the memristor state operating point X, respectively. In each plot, the state operating points along the red (blue) branches are unstable (stable) under voltage control, as discussed in section 2.2. Importantly, the resistance R 2 is negative throughout the red branch, i.e., for all X-values in the range [351, 1, 006], which corresponds to the entire NDR region of the memristor DC current-voltage characteristic of Figure 2C. Inserting the expression for d from Equation (23) into the formula (28) for R 1 , the device instantaneous resistance 28 R ≡ G −1 may be simply obtained via the resistance of the purely resistive branch in the circuit of Figure 8B, i.e., Additionally, the small-signal resistance r of the threshold switch may be computed as the parallel combination of the 28 By device instantaneous resistance we intend here its memristance. two resistances in the small-signal equivalent circuit model of Figure 8B, i.e., Y m (s) admits a zero s z,Y m and a pole s p,Y m , respectively, located at Figure 12 illustrates the pole-zero diagram of the local admittance Y m (s) of the NbO volatile memristor from NaMLab using a blue (red) color in either of the PDR regions (in the NDR region). While the zero from Equation (33), shown through a dash-dotted line, is negative for all the memristor state bias points within the set X ∈ [X a , X b ] = [253, 1, 722], the pole, located as specified in Equation (34), and depicted by means of a solid line, assumes positive values across the NDR region, i.e., for X ∈ (X 1 , X 2 ) = (351, 1, 006), holding the opposite sign in the lower PDR region, i.e., for X ∈ [X a , X 1 ) = [253, 351), and in the upper PDR region, i.e., for X ∈ (X 2 , X b ] = (1, 006, 1, 722]. REMARK 6. The analyses in sections 2.2 and 2.3 have revealed that, without the series resistor, i.e., for R s = 0 in the circuit of Figure 8A, any bias point Q m = (V m , I m ) lying on the NDR region of the memristor DC current-voltage characteristic is unstable under voltage control. This may be inferred also by observing that the pole s p,Y m of the device local admittance sits on the RHP for each bias point of this kind. Moreover, it is instructive to note that the pole s p,Y m of the device local admittance Y m coincides with the eigenvalue λ of the linearized form of the memristor state Equation (3), with state evolution function expressed by Equation (5), around the same operating point, i.e., recalling that, for R s = 0 in the circuit of Figure 8A, the voltage V m across the memristor is just a constant, as established by the DC source, where the latter equivalence descends from Equations (20), (29), (30), and (34). It follows that the locus of the eigenvalue λ vs. the state operating point X coincides with the diagram of the pole (34) of the device local admittance Y m (s), shown via a solid line in Figure 8.
Interestingly, inspecting the formula of the local admittance Y m of the combined memristor, consisting of the series combination between the linear resistor R s and the threshold switch, about the respective operating point Q m = (V m , I m ), with V m = V m +R s ·I m , and I m = I m , i.e., it is easy to verify that, as expected from the investigation from section 2.2, its pole s p,Y m , expressed by resides on the left half of the complex plane (LHP) as long as the resistance R s of the series resistor in the biasing circuit shown in Figure 8A is chosen so as to meet the constraint (13), where r| Q m is the threshold switch small-signal resistance r, expressed in (32) as a function of the parameters R 1 and R 2 of the smallsignal equivalent circuit shown in Figure 8B, and evaluated at the associated operating point Q m = (V m , I m ). It is worth to point out that the pole s p,Ym of the combined device local admittance Ym about Q m coincides with the eigenvalueλ of the linearized form of the memristor state Equation (3), with state evolution function expressed by Equation (5), around the corresponding threshold switch state operating point X, i.e., recalling that, for R s = 0 in the circuit shown in Figure 8A, the voltage across the memristor is a function v m = v m (x) of the memory state x as dictated by the voltage divider formula (11), where the last equivalence descends from Equations (20), (21) PDR (NDR), positive (negative) differential resistance; LP (LA), local passivity (activity); EOC, edge of chaos. Under current control, the memristor is found to converge toward one and only one globally asymptotically stable operating point Qm for each Im value. Under voltage control, the memristor is found to converge toward one and only one globally asymptotically stable operating point Qm provided the DC stimulus is chosen outside of the NDR range Vm ∈ (V m,2 , V m,1 ) (see the caption of Figure 2 for details).
On the other hand, if Vm falls within this range, the memristor exhibits bistability, and, depending upon the initial condition, may be asymptotically found in one of two possible locally stable operating points, which lie along distinct PDR branches of the DC currentvoltage characteristic.PDR (NDR), positive (negative) differential resistance; LP (LA), local passivity (activity); EOC, edge of chaos. Under current control, the memristor is found to converge toward one and only one globally asymptotically stable operating point Qm for each Im value. Under voltage control, the memristor is found to converge toward one and only one globally asymptotically stable operating point Qm provided the DC stimulus is chosen outside of the NDR range Vm ∈ (V m,2 , V m,1 ) (see the caption of Figure 2 for details). On the other hand, if Vm falls within this range, the memristor exhibits bistability, and, depending upon the initial condition, may be asymptotically found in one of two possible locally stable operating points, which lie along distinct PDR branches of the DC current-voltage characteristic. lying on the NDR region of the one-port DC current-voltage characteristic resides on the RHP, endowing Q m with an unstable character. The device is locally active at any bias point of this kind, in view of condition (1) from Remark 5. Moreover, in regard to the blue branches in the DC I m -V m locus of Figure 2C, expressing Y m (s) from Equation (27) in the Fourier domain, i.e., as , and (39) given that, as it is easy to demonstrate, ℜ{Y m (jω)} is strictly positive therein (see, e.g., Figures 13A-C, respectively, show the loci of ℜ{Y m (jω)} vs. ω, ℑ{Y m (jω)} vs. ω, and ℑ{Y m (jω)} vs. ℜ{Y m (jω)} for the state operating point X = 267), the voltage-controlled device is stable and locally passive at any PDR bias point, since none of the conditions in Remark 5 holds true. All in all, as summarized inTable 2, under voltage control the memristor device is locally passive throughout each of the two PDR branches of the I m -V m locus, while it is locally active and unstable at each operating point on the NDR region of the DC characteristic.
However, as shown in section 3.2, any NDR operating point Q m = (V m , I m ) of the voltage-controlled memristor can be stabilized by inserting a linear resistor, with resistance R s satisfying the inequality (13), in series with it. In fact, as known in memristor theory (Chua, 1971), this step effectively yields another voltage-controlled memristor, which we called combined memristor, and it is composed of the series connection between the resistor and the threshold switch, and is stable at the respective operating point Q m = (V m , I m ), where V m = V m + R s · I m , and I m = I m . Moreover, the voltage-controlled combined memristor is locally passive at any bias point Q m associated to a threshold switch operating point Q m , which is stabilized via FIGURE 15 | DC current I m ≡ I m -voltage V m = V m + R s · I m loci of the combined memristor for V s = 2.9 V and two distinct valued associated to the resistance R s of the series resistor, specifically 10 (dashed magenta curve), and 25 (dash-dotted green curve). The DC I m -V m locus of the threshold switch is also shown for reference using the red (blue) color and the solid line style for the NDR (PDR) branch, which, as studied in section 2.2 is unstable (stable) under voltage control. Note that the small-signal resistancer of the combined memristor, expressed byr = Y −1 m (0) = (R −1 s + r −1 ) −1 , is strictly positive only in the scenario where the value of 25 is assigned to R s . In fact, only in this case R s satisfies the condition (15), given that, with reference to Figure 3, for our threshold switching devicer, defined in Equation (16), is found to be equal to 21.43 at X = 411.
an opportune choice of the parameters V s and R s in the biasing circuit of Figure 8A. This follows from the fact that the real part ℜ{Y m (jω)} of the combined memristor local admittance Y m (jω), which is derived from Equation (36) by replacing the Laplace variable s with the Fourier variable jω, and is found to be described by results to be strictly positive across the entire range of real angular frequency values under the constraint (13), which prevents condition (4) from Remark 5 to apply. As an example, Figures 14A,B, respectively, depict the real and imaginary parts of the combined memristor local admittance Y m (jω) about the operating point Q m = (V m , I m ) = (2.9 V, 5.948 mA), corresponding to the threshold switch state operating point X = 478 and for the R s value of 330 , which meets the condition (13). Plotting Im{Y m (jω)} against Re{Y m (jω)}, on the basis of these two graphs, yields Figure 14C, where arrows indicate the direction of motion of the trajectory point as ω increases from −∞ to ∞. Interestingly, choosing a resistance R s , satisfying the inequality (15), in which for our devicer, as defined in Equation (16), and amounting to 21.43 at X = 411, denotes the largest modulus of the threshold switch differential resistance across its entire DC locus NDR region, the combined memristor is found to feature a strictly PDR. This is demonstrated graphically in Figure 15, showing the DC current I m ≡ I m -voltage V m = V m + R s · I m characteristics of the combined device in a couple of distinct scenarios, specifically for R s set to 10 , where the condition (15) is not satisfied (dashed magenta curve), and to 25 , where the constraint (15) is met (dash-dotted green locus), respectively, besides the DC I m -V m locus of the threshold switch, depicted in solid line style, and using the red and blue colors for the NDR and PDR branches, respectively.
All in all, under the constraint (15), withr defined in formula (16), the combined memristor is stable and locally passive along its entire DC I m -V m locus, since in these circumstances none of the 4 conditions from Remark 5 may ever apply at any of its bias points (the green dash-dotted DC current-voltage characteristic, which is illustrated in Figure 15 for R s = 25 , is exhibited by a combined device of this kind). On the other hand, in case the constraint (13) does not hold true along part of threshold switch NDR branch, then, similarly as it is the case for the threshold switch itself, also the DC characteristic of the voltage-controlled combined memristor would feature a region endowed with negative slope (the magenta dashed DC current-voltage characteristic, which is illustrated in Figure 15 for R s = 10 , is exhibited by a combined device of this kind), and similar conclusions, as drawn above for the operating regimes of the voltage-controlled NaMLab micro-structure, would apply to the resistor-NbO device series combination under voltage control. More specifically, in these circumstances, the voltage-controlled combined memristor would be locally passive along either of the two PDR branches of the DC I m -V m locus, while it would be locally active and unstable, in view of condition 1 from Remark 5, , with arrows indicating the evolution of the trajectory point along the Nyquist plot as the angular frequency increases from −∞ to +∞. The real part of the local impedance is negative for ω ∈ (ω l,Zm , ω r,Zm ), where ω r,Zm = −ω l,Zm = 18.305 Mrad· s −1 . It follows that, under current control, the memristor is locally active and stable at the state operating point X = 478, and, as a result, it is said to poised on the EOC therein. throughout its DC characteristic NDR branch, which corresponds to that part of the NDR region of the threshold switch DC I m -V m locus, where the condition (13) is not met.
Importantly, as revealed via the investigation of section 2.2, under current control the NbO memristor is stable at each operating point Q m residing along the NDR region of its DC I m -V m locus. Here it is of interest to derive the memristor local impedance Z m , which is simply expressed by the inverse of the device local admittance Y m of Equation (27). In the Fourier domain, Z m is given by At any operating point Q m along the entire NDR region of the device DC I m -V m characteristic, R 2 is strictly negative, while R 1 + R 2 is strictly positive. It follows that the real part ℜ{Z m (jω)} of the memristor local impedance goes negative within the angular frequency range For example, Figures 16A,B illustrate the real and imaginary parts of the memristor local impedance Z m (jω) about the operating point Q m = (V m , I m ) = (0.937 V, 5.948 mA) as a function of the angular frequency ω, respectively. Here, ℜ{Z m (jω)} < 0 for the angular frequency range specified in Equation (45), where ω r,Z m = −ω l,Z m = 18.305 Mrad· s −1 , as indicated also in the corresponding Nyquist plot, illustrated in Figure 16C. All in all, as reported in Table 2, under current control, the NaMLab NbO threshold switch is locally passive at each bias FIGURE 17 | Current compliance-constrained response of the NbO memristor to a quasi-DC voltage stimulus. (A) Strictly positive triangular voltage waveform v s of amplitudev s = 1.45 V and period T = 9 s falling directly across the device only when the latter is out of the compliance regime, and time waveform of the memristor voltage, which, when the current through the micro-structure attains the compliance level, descends abruptly to a fixed value, keeping unchanged thereafter till the time instant, at which the triangular stimulus descends below it. (B) Memory state response to the current-constrained quasi-DC voltage excitation test. (C) Current flowing through the device under the compliance-constrained quasi-static test. The red and blue waveforms in (A,C) were respectively extracted from experimental measurements performed at a chamber ambient temperature T amb of −20 • C and from a numerical simulation of the model, consisting of the DAE set (3) and (4), with state evolution and memductance functions, respectively, expressed by Equations (5) and (6), under nominal conditions, and of the DAE set (7) and (8), with state evolution and memristance functions, respectively, expressed by Equations (9) and (10), with i m = I c = 5 mA, in compliance mode, for an initial condition x 0 x(0 s) equal to 253.15. The green waveforms in (A,B) report further results from the model simulation. Plotting the memristor current i m from (C) against the source voltage v s from (A), i.e., against the voltage, which would fall across the micro-device in case it would never operate in compliance mode, results in the quasi-static current-voltage locus shown in Figure 19 through a blue dotted (magenta dashed) curve, as extracted via measurements (through a model numerical simulation). Six numbered arrows, referring to the magenta dashed curve, show the evolution of the trajectory point (v s , i m ) over time in one input cycle. No point exists along the vertical line numbered 2 (5), when the micro-structure is abruptly transitioning into (out of) the compliance regime, when the locus visits data paths 3, and 4, i.e., the vertical lines are only drawn for visualizing better the sequence of events preceding and following the current-limited phase (see also Figure 20B on a compliance-free quasi-DC voltage excitation test with R s = 0 ). With respect to the numerical simulation result, in case i m from (C) were plotted against v m from (A) in Figure 19, the resulting locus would differ from the i m -v s characteristic only over the compliance phase, when the only trajectory point from the arrowed path 3 → 4 of the magenta dashed curve, which one would observe in this case after Q represents the unique intersection point between the device DC I m -V m locus, shown in black in Figure 19, and the horizontal load line I m = I c associated to the compliance phase, when the quasi-DC voltage source across the threshold switch acts as a DC current source of value I s = I c ). point on either of the two PDR branches of the DC currentvoltage characteristic, while it is locally active and stable, i.e., it is poised on the EOC, throughout the NDR region of the I m -V m locus.

QUASI-STATIC BEHAVIOR OF THE MICRO-SCALE DEVICE
This section is devoted to explain the difference between the quasi-DC and the DC behaviors of the memristor device so as to clarify once and for all some of the misconceptions, which are often encountered in the literature in this regard. The response of the threshold switch to a slowly varying purely AC periodic stimulus, typically referred to as quasi-static or quasi-DC input, may either deviate from or accurately mimic the DC behavior depending upon the nature of excitation waveform, i.e., whether it is in voltage or in current form. Figure 17 shows both experimental results (in red) and model solutions (predictions of measurements in blue and further numerical results in green) on the NaMLab memristor dynamics in response to a strictly positive purely AC periodic quasi-static voltage stimulus of triangular shape, amplitudev s = 1.45 V, and period T = 9 s 29 , 29 Given that, as anticipated earlier, it is reasonable to associate the device memory state x to its internal temperature T expressed in units K, the initial condition x 0 = 253.15 corresponds to T 0 T(0 s) = −20 • , which coincides with the ambient temperature T amb set in the chamber hosting the threshold switch during the lab test.  (3) and (4), with state evolution and memductance functions expressed by Equations (5) and (6), respectively, and under the initial condition x 0 = 253.15. Plotting the memristor current i m from (D) against the memristor voltage v m from (C), the resulting AC i m -v m locus, shown in Figure 19 in the green (yellow) color, as extracted through measurements (as derived from a numerical simulation of the model), matches rather well the threshold switch DC I m -V m locus, drawn in black in the same figure, despite the stimulus frequency is well beyond 0 Hz. Given that the threshold switch behaves similarly as under DC excitation, the 10 kHz AC input voltage in (A) may be practically considered as a quasi-static stimulus as far as the dynamics of its memory state are concerned. The agreement between the device quasi-static and DC current-voltage loci in this scenario is expected from the analyses of sections 2.3 and 3.3, since the voltage-based quasi-DC stimulus is applied across the combined memristor and the resistance R s is chosen so as to stabilize the entire NDR branch of the threshold switch DC current-voltage characteristic.
as shown in plot (A), for x 0 x(0 s) = 253.15, and under current constraint measures. In this regard, in order to prevent an irreversible damage to the memristor physical structure during the device abrupt off-to-on resistance switching process, the maximum current flowing through the micro-scale device, was limited to a compliance value I c of 5 mA both in the lab and in the model numerical simulation. at compliance clarifies of the underlying characterization test, especially for the purpose of comparing the threshold switch response to approximately static excitations to its behavior under DC stress. In the remainder of the paper, a generic point of this kind is referred to as quasi-DC point so as to differentiate its name from the one-specifically DC operating or bias point-attributed to a generic point Q m,i along the device DC I m -V m characteristic.  Figure 17 for more details-until each time instant at which, during an abrupt off-to-on threshold switching process, the current i m through the micro-structure attained a compliance level I c set to 5 mA, while turning into a DC source of current I s = I c throughout each compliance mode phase. Note that, in accordance with similar current-limited quasi-DC loci reported in the literature, the horizontal axis for the blue dotted and magenta dashed characteristics shows the voltage, which would fall across the device in case it would never enter the compliance domain, i.e., in case it would always keep in the nominal operating mode, while, as explained in the text, the actual voltage dropping between the two memristor terminals under the current-limited regime is governed by the current-controlled Ohm law (8), with memristance R defined in Equation (10) = (0.954V, 5 mA), throughout the compliance mode phase, instead of the data path 3 → 4 appearing when the horizontal axis shows the triangular excitation signal v s  (no data point exists along the vertical lines numbered 2 and 5, which simply show the abrupt device set and reset transitions, respectively). Green (yellow) solid curve: AC i m vs. v m characteristic of the NbO device extracted in a lab experiment (from a numerical simulation of the model), as the series combination between the memristor and a resistor with resistance R s = 330 is excited by a purely positive periodic triangular voltage signal v s of amplitudev s = 4 V and frequency f = 10 kHz (see Figure 18 for details). As the experiment (model numerical simulation) reveals, the green (yellow) solid curve approximates with good accuracy the black-colored DC I m -V m characteristic.
why, as may be inferred by inspecting plot (A) in Figure 17, the memristor voltage follows the 0.11 Hz-periodic triangular stimulus only as long as the micro-structure operates out of the compliance regime, while it abruptly decreases to the voltage of the only possible device bias point for i m = I c , as soon as the device sets into the compliance mode, keeping unchanged afterwards, till the periodic voltage stimulus decreases below the constant memristor voltage level V m,B , i.e., the abscissa of Q (quasi−DC) m,B ).
REMARK 7. Basically, the periodic voltage generator v s , appearing in parallel to the threshold switch, begins to source a DC current I s , equal to the earlier specified upper bound I c , as soon as the device current is about to exceed the compliance level during the abrupt turn-on process of the micro-structure, and keeps operating in this "DC current mode" as long as the periodic voltage waveform, which it would have sourced continuously in case no current limitation strategy were set into place, is about to decrease below the voltage of the only possible DC operating point, which the device may admit throughout the compliance phase. In order to reproduce the device behavior in compliance mode using our mathematical description, as the current flowing through the micro-structure attains the specified threshold I c , the voltage-controlled device DAE set (3) and (4), with state evolution function g(·, ·) expressed by Equation (5) and memductance function G(·) described via Equation (6), is recast as the model of a current-controlled generic memristor, namely (7) and (8), with state evolution function and memristance function, respectively, expressed by Equations (9) (5), which simply shows the device abrupt set (reset) transition. The PDR branches (NDR branch) of the device DC current-voltage characteristic are (is) plotted in dashed line style and magenta (green) color. A triplet of load lines, in dashed-dotted line style and different colors, is also depicted to indicate, once again, that only their crossings with intrinsically stable PDR parts of the device DC I m -V m characteristic appear also as points of the quasi-static i m -v m locus in blue solid line style. As expected from the analysis in section 2(b), the quasi-static locus visits none of the DC operating points, lying on the green dashed NDR branch, since, under voltage control, the latter may not be stabilized without a series resistor. Given that the vertical lines numbered 2 and 5 are data free, the quasi-DC locus is in fact composed of two disconnected branches, which are separated by the entire NDR branch of the DC locus. Now, the uppermost (lowermost) quasi-DC point of the lower (upper) branch of the blue solid curve, indicated via a blue square marker, is located at Q in Equation (16), was found to be equal to 21.43 at X = 411 for our threshold switch, is now inserted between a quasi-DC voltage stimulus and the memristor, the latter undergoes dynamics, which closely approximate its DC behavior. With reference to Figure 18, in which the blue and red color is, respectively, adopted to visualize the lab measurements and their model predictions, when a strictly positive purely AC periodic triangular voltage waveform 32 v s of amplitudev s = 4 V and period T = 0.1 ms, as shown in plot (A), is applied to the series combination of a series resistor of resistance R s = 330 and the NamLab NbO memristor sample, the state, voltage, and current of the threshold switch exhibit the time waveforms illustrated in plots (B), (C), and (D), respectively. Here, where it is the series resistance which acts as memristor current limiter, plotting the memristor voltage against the memristor current-see the green (yellow) locus in Figure 19 in regard to the experimental result (the model numerical simulation)-replicates precisely the threshold switch DC I m -V m characteristic, drawn in black in the same figure. The agreement between the quasi-static and DC behaviors of the voltage-controlled threshold switch in this case descends from the fact that the chosen value for the resistance R s of the series resistor stabilizes the entire device DC locus NDR branch, which, on the other hand, was left unstable, except for 32 Despite the input frequency is not close to 0 Hz in this case, as far as our micro-scale device is concerned, the input voltage waveform of Figure 18A may be practically considered a quasi-DC stimulus. the compliance-controlled operating point Q m,B , in the currentconstrained quasi-DC voltage excitation test shown in Figure 17. In case the linear resistance R s , set in series to the threshold switch so as to stabilize one of its NDR operating points, according to constraint (13), is however not sufficiently large to satisfy condition (15), part of the NDR region of the device DC I m -V m locus will keep unstable. Let us gain some insight into the effects of the partial stabilization of the device DC locus NDR branch on its response to a compliance-free quasi-static voltage stimulation.
REMARK 8. Figure 20A shows how the small-signal resistance r| v m =V m of the threshold switch changes with its DC voltage throughout the NDR region, where V m assumes values in the range (V m,2 , V m,1 ) = (0.826, 1.007)V, as discussed in the derivation of the DC X-V m , X-I m , and I m -V m characteristics of the volatile memristor [refer to Figures 2A-C from section (2)(b), respectively]. Importantly, in case the series resistance R s is set to a certain value lower than |r|, which, as specified in Equation (16), is equal to 21.43 at V m = 0.981 V, the graph in Figure 20A may be interrogated to derive the range of memristor DC voltage values, at which the operating points of the NbO micro-memristor keeps unstable. For example, with R s , respectively equal to 0, 5, 10, 15, and 20 , the open set of unstable NDR V m values is in turn (0.826, 1.007) V, covering the entire NDR region of the device DC locus, (0.865, 1.007), (0.898, 1.006), (0.928, 1.003), and (0.961, 0.994) V. Employing a numerical simulation of the polynomial model, Figure 20B shows via a blue solid curve the Last but not least, inserting a quasi-static current through the memristor, the resulting AC i m vs. v m locus is found to resemble closely the device DC I m -V m characteristic. This is shown by means of a numerical simulation of the DAE set (7) and (8), with state evolution and memristance functions, respectively, expressed by (9) and (10) and for x 0 = 253.15. As illustrated in Figure 22A, a quasi-DC strictly positive AC periodic triangular current i s , of amplitude 15 mA and period T = 9 s, is let flow through the NbO memristor. It follows that the state and voltage of the device oscillate over time as depicted in Figures 22B,C, respectively. The resulting memristor 34 As indicated for four V s values in (a), the intersections between a load line and the device DC locus appear as quasi-DC points along the blue solid curve if and only if these crossings lie along either PDR branch or along the stabilized parts of the NDR branch of the device DC locus. Finally, numbered arrows and data-free set/reset transitions, featuring the same slope as the respective load lines, are shown only in plots (A) and (B), since, given the increasingly short horizontal distance between the blue square markers as R s is assigned larger values, they would create clutter in plots (C) and (D). AC current vs. voltage locus, highlighted with the blue color in plot (Figure 22D), approximates accurately the device I m -V m characteristic, reproduced in magenta in the same figure. This was expected from the investigation of section 2.2, since the entire NDR branch of the memristor DC locus is stable under current control.
Before summing up the main results of this pedagogical article, it is worth to point out that the NbO micro-memristor exhibits the fingerprint of all memristors, namely the pinched hysteresis loop (Chua, 2014) on the voltage-current plane. Figure 23, based upon numerical simulations of the proposed polynomial-based model, depicts how the steady-state i m vs. v m locus evolves upon exciting the device with an AC source of the form i s =î s · sin(2 · π · f · t) withî s = 15 mA, as the frequency is swept stepwise across the set of values {10 4 , 10 5 , 10 6 , 4 · 10 6 , 10 7 , 10 8 , 10 9 } Hz. Interestingly, each loop is tangential in the origin (Biolek et al., 2011), as highlighted for a representative scenario, specifically for f = 10 6 Hz, by showing the direction of motion of a trajectory point along the associated characteristic over time (see the sequence of arrows on the red locus). For the lowest frequency from the aforementioned set, the locus is similar to a quasi-static characteristic under bipolar current control (compare it with the one in Figure 22D, where the current stimulus is strictly positive). As the input frequency is increased, the pinched hysteresis loop opens up and differentiates more and more from the DC locus. After a FIGURE 23 | Pinched hysteresis loops (Chua, 2014) of tangential type (Biolek et al., 2011), emerging at steady-state on the v m -i m plane under the application of an AC source, generating a sine wave current of the form i s =î s · sin(2 · π · f · t) directly across the NbO memristor, forî s = 15 mA, as the frequency is stepped across the set of values {10 4 , 10 5 , 10 6 , 4 · 10 6 , 10 7 , 10 8 , 10 9 } Hz. These results were obtained by numerical simulation of the proposed polynomial-based DAE set (3) and (4), with g(x, v m ) and G(x) expressed by Equations (5) and (6), respectively, and for an initial condition fixed to x 0 = 253.15. For the scenario associated to the lowest input frequency in the aforementioned set, the locus resembles closely a quasi-static characteristic under current control, similarly as the plot of i m vs. v m in Figure 22D, with the only difference that here the input assumes also negative values. As the frequency is increased, first the overall loop lobe area is found to increase, while, concurrently, the shape of the characteristic differentiates itself more and more from the DC I m vs. V m locus (arrows are superimposed on top of one of the characteristics, specifically the red one observed for f = 10 6 Hz, to provide evidence for the tangential nature of the loop). Then, after a certain threshold frequency, as expected of all memristors, the pinched hysteresis loop begins to shrink monotonously with the frequency (Chua, 2014). For very high frequencies the locus reduces to a straight line, as expected of all generic memristors (note that, differently from what happens for ideal and ideal generic memristors, the slope of the linear i m -v m characteristic in this limiting cases depends upon the input amplitude) (Chua, 2015). certain point, however, the loop lobe area begins to decrease progressively, as expected of all resistance switching memories (Chua, 2014), until, for the largest frequency value, the locus reduces to a straight line, as is the case for all generic memristors (Chua, 2015).

DISCUSSION
Miniaturized memristor devices based upon certain materials, such as niobium dioxide, are able to amplify infinitesimal fluctuations in energy, and, when they exhibit such an impressive and peculiar capability, they are said to operate in the locally active regime. Since the potassium and sodium ion channels in biological axon membranes (Hodgkin and Huxley, 1952) are locally active memristors (Chua et al., 2012), which provide an essential contribution for the emergence of the all-ornone neuronal spiking behavior, it is clear that solid-state resistance switching memories, which admit a negative smallsignal resistance over a range of operating points, which, as explained in this manuscript, constitutes a signature for their capability to enter the LA domain, will play a major role for the development of basic electronic building blocks of novel biomimetic neuromorphic networks. There have already been a few promising attempts to adopt these kinds of memristor physical realizations (Pickett and Williams, 2012) for the electronic implementation of biological neurons, the so-called neuronal memristors, or neuristors for short Yi et al., 2018), which have been further combined through various coupling arrangements to form memristive cellular automata endowed with computational universality , and memristive cellular neural networks (M-CNNs), which, supporting the emergence of dynamic patterns (Weiher et al., 2019;Demirkol et al., 2021), may be employed to solve complex non-deterministic polynomial-time (NP)-hard optimization problems, such as the challenging task of coloring the vertices of an undirected graph (Weiher et al., 2021). In this article, we employed powerful techniques from non-linear circuit (Chua, 1987) and system Corinto et al., 2020) theory as well as rigorous concepts from the theory of complexity to gain a thorough understanding of the non-linear dynamics of a locally active memristive microstructure from NaMLab. Given the inherent instability of the NDR branch of the device DC current I m -voltage V m characteristic under voltage control, the condition for the stabilization of any operating point Q m = (V m , I m ) along it has been discussed from different viewpoints: (1) using a circuit-theoretic approach with the load line method; (2) applying a system-theoretic graphical tool, enabling the analysis of first-order systems, and known as DRM (Chua, 2018); (3) pursuing a classical linearization analysis of the memristor state equation in the time (frequency) domain on the basis of the eigenvalue (the pole of the device local admittance) about the operating point. The application of the LA theorem (Chua, 2005) to the device small-signal circuit model, extracted from the expression of the memristor local admittance, has subsequently allowed us to tabulate all the possible device operating modes, specifically the locally passive, the locally active and unstable, and the locally passive and stable regimes, the latter being typically referred to as EOC domain, depending upon its bias point as well as upon the nature of the control signal, being in voltage or current form. The availability of a full picture of the memristor behavior, derived by means of a rigorous theoretical analysis corroborated by experimental measurements on device samples, is instrumental for the future development of a systematic approach to design bio-inspired oscillatory networks. Finally, it is worth pointing out that this research provides clear evidence for the significant role that non-linear circuit and system theory assumes for gaining a deep insight into the operating principles of inherently non-linear memristive devices and circuits, which constitutes a crucial prerequisite for the development of a rigorous technique, aware of all the key system parameters in action, to design variability-tolerant neuromorphic electronic hardware.

CONCLUSIONS
In order for complex phenomena, e.g., the generation of action potentials in neuronal axon membranes, to emerge in biological systems, some of their essential units have to display the capability to enter a locally active operating mode, where they would be able to amplify the small-signal, upon the provision of a suitable DC energy source (Ascoli et al., 2020a). For example, the basic unit in the neuronal axon membrane may operate in the LA domain, and, most remarkably, in its "pearl" subdomain, referred to as EOC, and hosting the germ of complexity. This is possible because the membrane accommodates two voltage-controlled volatile memristors, namely the potassium and sodium ion channels 35 , which may boost local fluctuations in energy when biased on the NDR regions of their DC currentvoltage loci (Chua et al., 2012). Recently, several research groups have presented solid-state volatile memory devices with DC characteristics including well-defined NDR regions (Pickett and Williams, 2012). Biasing any of such devices in some point, where the respective DC current-voltage locus features a negative slope, the memristor is said to operate in the LA regime. Superimposing a small-signal on top of the DC operating point, the locally active memristor may operate similarly as a MOS transistor biased in the saturation region, amplifying the local fluctuations at the expense of some DC power supply. Besides opening up the opportunity to design transistor-less small-signal amplification circuits as well as oscillatory networks, in which the emergence of spatiotemporal phenomena (Weiher et al., 2019) may be exploited to solve complex optimization problems (Weiher et al., 2021), the adoption of locally active memristors in electronics may also allow an accurate reproduction of the non-linear dynamics of potassium and sodium ion channels in innovative 35 It is instructive to observe that even the ion channels in the human heart (Zhang et al., 2020) are volatile locally active memristors. neuromorphic hardware . In this article, we gained a deep insight into the non-linear dynamics of a NbO micro-scale memristor exhibiting an NDR region along the DC characteristic. The application of powerful techniques from nonlinear circuit and system theory (Chua, 1987), and the adoption of methods from the theory of local activity (Chua, 2005), allowed us to understand the mechanisms behind the operation of this voltage-controlled volatile memristor from NaMLab in the LA regime to classify all the admissible operating modes of the threshold switch, and to clarify, once and for all, under which conditions the response of the micro-scale device to quasistatic stimuli matches its behavior under DC stress. Importantly, experimental measurements on a device sample fabricated at the premises of NaMLab GgmbH confirm the theoretical results, providing further support to the significance of this research contribution, which sheds light on the invaluable role that nonlinear system theory plays in understanding the rich non-linear dynamics of memristors.

DATA AVAILABILITY STATEMENT
The raw data supporting the conclusions of this article will be made available by the authors, without undue reservation.

AUTHOR CONTRIBUTIONS
AA has conceived the main idea of the paper and written the entire manuscript. AA and SS have developed the device model. AA and SS performed the experimental measurements. AA and ASD have derived the device small-signal model, and applied the LA theory to the resulting circuit representation. RT, TM, and LC have provided a precious guidance throughout the development of the research work. All authors contributed to the article and approved the submitted version.