Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs), remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET) offers electronic-optical hybridization at the component level, which can continue Moore's law to the quantum region without requiring a FET's fabrication complexity, e.g. a physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x10^6 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses). Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

Text: As basic electronics building block, a field-effect transistor's (FET's) primary switching function is widely used in both logic and memory chips. A typical FET is a three-terminal device consisting of source (S), drain (D), and gate (G) contacts -where the S-D conductivity is modulated to realize on and off states by applying a voltage or an applied electric field through G. 1 Although FETs have evolved structurally from early planar to current 3D geometries in parallel with the continual shrinkage of its lateral size, the basic operation principle remains the same, which leads to ever greater fabrication complexity, and ultimately to challenges in gate fabrication and doping control. [2][3][4][5][6] Various new technologies, such as FinFET, 2, 7 and tunnel-FET, 8 have been developed in recent years to enable the continuation of Moore's law, 9 but further development with current technologies are uncertain. 10 Other options are being explored as alternatives, which include semiconductor nanowire (SNW) based FETs, [11][12][13] FETs comprised of 2D materials, 14,15 and FETs with sophisticated gate structures, 16 such as multiple independent gates 3, 5 or a gate with embedded ferroelectric material. 17 There is, however, no clear pathway for overcoming a FET's intrinsic physical limitations [18][19][20] dictated by its operation mechanism, such as random dopant fluctuations 6 and gate fabrication complexities, 21 and no viable rival technology currently exists. We offer a competitive alternative with additional unique functionalities. The light-effect transistor (LET) is a two-terminal device composed of a metal-semiconductor-metal (M-S-M) structure, where each M-S junction serves as either the S or D contact, and the two contacts are separated by a semiconductor nanostructure channel. Fig. 1 contrasts SNW-based LET and FET structures to reveal the apparent structural simplicity offered by a LET -no physical gate is required. A LET's operation mechanism is distinctly different from a FET in two regards: (1) the S-D conductivity is solely modulated by light or an optical frequency electromagnetic field, which contrasts a FET's electrostatic control through an applied DC voltage, and (2) current carriers are generated through optical absorption rather than by thermal activation of dopants. In other words, a LET employs optical gating based upon the well-known photoconductive mechanism 22 that has typically been of interest in photo-detection. Inherent advantages stem from a LET's simplistic architecture, which include (1) eliminating gate fabrication complexity, and (2) avoiding difficulties with doping control. These attributes remove the two primary challenges or intrinsic limitations facing conventional FETs in regards to their continuous down scaling to the quantum regime, 23 and in the meantime, they offer the potential for reduced fabrication costs. While a LET's most basic application emulates a FET when it operates under onebeam illumination as in a photo-detector, it offers functions not readily achievable by either a FET 24 or a photo-detector, 25,26 when it operates differently than a typical photodetector, e.g., when responding to multiple independent light beams.
Light-induced electrical conductivity change is a well-known phenomenon typically used for photo-detection. In fact, SNW devices structurally similar to our LET have been investigated as photo-detectors. 25,26 At first glance, it may appear that a LET simply employs a photo-detector's switching function to emulate a FET. In reality, most photo-detectors lack desirable FET-like characteristics and are therefore unsuitable for LET use. It is therefore important to understand the differences between a photo-detector, LET, and FET to appreciate the LET's novelty. Photo-detection typically relies upon a pn junction-based device, because it usually offers superior performance over a simpler M-S-M device based on the photoconductive mechanism. This arises from the M-S-M structure typically requiring a larger bias to drive carriers through the S region. 1,22 Significantly, a p-n junction based photo-detector has a distinctly different I-V characteristic under illumination from a photoconductive based one, and only the latter can offer a light I-V resembling that of a FET with gate voltage on. The photoconductive mode's disadvantage is eased through reduced device dimensions, as demonstrated by SNW-based photo-detectors, 25,26 and the LET application in this work. Its structural simplicity should provide further advantages at the genuine nanoscale. We note that photo-detector structures that are difficult to dope may also employ a M-S-M structure. 1,22 Therefore, a LET does not employ a new device structure or mechanism. Its novelty stems from its stringent electrical and optical characteristics that can (1) replicate the basic switching function of the modern FET with competitive (and potentially improved) characteristics, and (2) enable new functionalities not available in modern FETs, as well as, allow new applications beyond those offered by conventional photo-detectors. While under single-beam illumination, a LET requires a high on/off ratio under optical gating, which resembles a FET under gate-voltage control or a photo-detector with high photoconductive gain. Despite this similarity, a LET should also be characterized for a pertinent FET parameter known as "subthreshold swing", which measures how much gate action is required to turn on the device, and is normally not of interest in photodetection applications. Under simultaneous multi-beam illumination, which is usually irrelevant for photo-detection, the multiple independent gating capability enables a LET to demonstrate previously unreported functions, such as optical logic (AND and OR) gates and optical amplification as an analog application. In contrast, multiple independent gating has been a very challenging task for FETs. 3 These unique functionalities are of great interest for optical computing and novel optical detectors. To summarize, LET novelty, in comparison to photo-detectors, is two-fold: First, LETs are characterized electrically in a very different manner than photo-detectors, as photo-detectors are not typically explored for electronic functions found in a FET. Second, LETs utilize their multi-beam response while a photo-detector does not. In comparison to FETs, a LET's gating mechanism is distinctly different from a FET's, which makes easy the LET's multi-gate capability, and allows a LET to offer functions beyond those in a typical FET.
Furthermore, a LET's frequency response or switching speed is limited by the carrier lifetime in its conducting channel. While this effect is shared with a FET, a FET's response is limited by its gate capacitance.
Our LET devices employ readily available CdSe SNWs. 27,28  CdSe's bandgap energy. 30 The inset overlays a PL map upon an optical image to demonstrate relatively homogenous SNW emission, and by extension, homogenous material quality across the SNW channel. In Fig. 2E, the output characteristic, S-D current Ids vs. S-D voltage Vds, is demonstrated for the device with and without light illumination using a halogen light, where illumination optically modulates or "gates" the electrical conductivity between dark ("off") and illuminated ("on") states. The Ids vs. Vds curves of the two states clearly resembles those of a FET's off and on states, 1 respectively, especially when Vds < ~7 V. LETs -being electrical-optical hybrid devices where an electrical field, Vds , and an optical field, Pg, together modulate the electrical output, Ids -differ from other optoelectronic devices, such as light-emitting devices (or solar cells) that require an electrical (or optical) input to generate an optical (or electrical) output. LET features far greater gating flexibility and ability than a FET. Optical gating through Pg(λg) has two basic control parameters: wavelength, λg, and power level, Pg, under one-beam CW operation, but it can be readily extended to other operation modes, for instance, multiple independent beams and pulsed illumination represented as Pg(λg1, λg2,…,λgN) and Pg(t,λg1, λg2,…,λgN), respectively. In this work, we first fully characterize LET output and transfer characteristics under one-beam CW operation with two illumination conditions: (a) illuminating the center of the SNW with a focused CW laser ("focused illumination") with an optical diffraction-limited spot size at wavelengths of 633, 532, 442, or 325 nm; and (b) illuminating the LET uniformly with "white light" from a halogen lamp ("uniform illumination"). Results for two devices, device 1 (D1) and device 2 (D2) with lengths of ~10 and ~5.5 µm and similar diameters (~80 nm), are presented to illustrate general LET properties, and to demonstrate the potential for characteristic tuning and optimization. The two devices were fabricated in essentially the same way. We then explore some unique functionalities under two-beam illumination that are not readily achievable with a typical FET.
Device dark currents reveal negligible reverse bias current and rectification (diode-like behavior) under forward bias, e.g. respectively. Differences between D1 and D2 indicate that a LET's characteristics may be tuned and optimized through material and device engineering. A large M-SNW contact barrier is generally desirable for producing small off state currents over the operation range, and can be optimized to maximize the on/off ratio. Note that current levels for different "gate" wavelengths in Figs. 3A-D showed considerable variations, which is fundamentally due to wavelength-dependent light-matter interaction effects, e.g. absorption and carrier dynamics, and illumination conditions, e.g. power density and beam size. This feature offers the unique LET advantage of flexibility in achieving gate functions compared to FETs.
The Ids-Vds curves in Fig. 3 may be understood qualitatively with the photoconductivity model proposed by Mott and Gurney. 22 The first plateau is associated with the "primary photoconductivity" which produces current as a result of photo-generated electrons and holes flowing through the nanowire under applied bias. A steady state condition is formed when just enough external carriers entering the nanowire through the electrodes replenish those leaving the device. The collection efficiency, Ψ, can be where w is the carrier's mean free path (which is proportional to the applied field), L is the nanowire's length, and x0 is the illumination site measured from the anode. This theory suggests a continuous photocurrent increase from Vds = 0 until saturation occurs at a sufficient Vds to produce w >> L ( Figure S1 for simulated Ψ vs. Vds curves). If all photons are absorbed, Ψ is equivalent to the quantum efficiency, ηQE, defined as Iph/(eNph), where Iph is the photoinduced current, and Nph is the number of absorbed photons. When current saturation occurs, ηQE = 100%. For instance, absorbing 2 µW of 620 nm light with ηQE = 100% yields a 1 µA current. As Vds approaches VD,on, a major Schottky barrier reduction 31,33 allows excess carriers to enter the nanowire through the electrode, which then produce a drastic Ids increase that allows ηQE >> 1. This simple picture is most applicable to D1. For LET's off-state energy consumption can be very low. For instance, the dark current is ~1 pA at Vds = 1.43 V with a corresponding static power consumption of ~1.5 pW, which is lower than a FET of similar length. 35 Significantly, the collection efficiency is expected to improve drastically at low Vds with nanometer-length devices ( Figure S1), which should further reduce the static power consumption and provide lower Vds than those demonstrated here. The maximum applied laser power is about 3 µW and corresponds to a power density of ~0.60 W/mm 2 , which is less than that delivered by an efficient light-emitting diode. 36 The actually used gate power is only about 10% of the applied power because the laser spot size is considerably larger than the nanowire diameter (Supporting Information for energy loss estimates). Reducing the beam size closer to the SNW's diameter could reduce Pg by at least a factor of 10, 37 and, as is well established in FET devices, reducing the channel length can reduce required the Vds ( Figure S1).
Enhanced efficiency and reduced energy consumption could significantly reduce thermal issues plaguing nanoscale FET-containing electronics devices. We note that FET has a thermal dynamic limit of S ≥ (kT/q) ln(10) = 60 mV/decade at 300 K, whereas for LET, SLET is extrinsic in nature through the dependence of w on the carrier density, which in turn depends on the defect density. Thus, SLET can be significantly improved by shortening conduction channel and perfecting the material quality. Truth tables for these logic operations and their proposed symbols are provided ( Figure S4).
Significantly, LET's do not require multiple switches or single-NW devices to realize complex logic functions, which could require fewer devices to perform identical or enhanced functionality. Thus LETs offer an additional pathway for achieving high device densities on a single chip.

Light-effect transistor (LET) with independent gating for optical logic gates and optical amplification
Jason K. Marmon 1-3 , Satish C. Rai

S1. Estimated Actual Power Absorption
Estimation of the laser spot size, and its area relative to the nanowire investigated to determine the actual power absorbed under different wavelengths.

S4. Collection Efficiency: Uniform and Focused Illumination
Quantum efficiency plots as a function of electron lifetime and nanowire length after Mott and Gurney 22 to demonstrate potential output characteristic changes from altering the optical gate or illumination position along the nanowire.

S5. LET Transfer Characteristics with 532 nm and Halogen Illumination
Two-beam point plots with data used to create contour plots in the main text.

S6. Non-linear Dual Beam LET Transfer Characteristics with 633 nm and Halogen Illumination
A two-beam illumination contour plot under another wavelength (633 nm instead of 532 nm) that demonstrates non-linear behavior.

S1. Estimated Actual Power Absorption
The laser spot size is estimated by the optical diffraction limit formula 1.22 λ /N.A., where N.A. is the numerical aperture of the microscope lens. The fraction of the laser power actually absorbed is estimated by taking the ratio of the nanowire diameter to the laser spot size.
The estimated ratios for the 632.8, 532, 441.6, and 325 nm lasers are 5.18, 6.16, 7.43, and 10.1% for a nanowire with an 80 nm diameter (device D1). For halogen illumination, the fraction of actual absorbed light is estimated using the ratio of the nanowire's cross section to the total illumination area. For the 50x LWD (10x MPLAN) objective lens, the illumination area is ~279 (~1450) µm 2 . The ratio for the 80 nm wide/10 µm long nanowire (D1) is ~3.2 10 -6 , and the power estimation for light actually absorbed is ~0.22 µW (which is comparable to that for the focused laser beam). All the illumination powers mentioned in the manuscript were applied powers, unless an actually absorbed power was explicitly stated.

S2. Nanowire Synthesis & Device Fabrication
CdSe nanowires were grown in a vertical array through gold-catalyzed chemical vapor deposition, as described elsewhere, 27

S3. Collection Efficiency: Uniform and Focused Illumination
In the photoconductive region that Mott & Gurney 22 refer to as "primary photoconductivity," the electron collection efficiency, Ψ , is equivalent to the quantum efficiency, QE η , assuming 100% absorption efficiency, and can be described with either Eqs. S1 or S2 for focused or uniform illumination respectively. Focused (uniform) illumination is when a single point (the entire length) of the nanowire is illuminated.
In Eq. S1, 0 x is distance from the illumination site to the anode electrode, L is the conducting channel's length, and w is the electron mean free path and is related to the applied electrical field, F , or voltage, V , through / w vFT vVT L = = . The variables v and T are the carrier mobility and carrier lifetime, respectively. Eqs. S1-S2 may be compared to provide additional insight into the two typical operation modes.  Fig. S1 indicates that two illumination modes yield comparable efficiency, and as a result, either focused or broad-area illumination could be reasonably implemented into a device, depending on the specific application need. An upper efficiency limit of 50% exists as only electrons are considered. In Fig. S1A, increasing the electron's mean free path by increasing carrier lifetime resulted in reaching a higher efficiency more rapidly, which suggests the ability to control current production at low applied bias. Fig. S1B indicates that nanowire length may also control the low bias current, where shorter nanowire devices produce larger currents. D1 and D2 were ~10. and ~5.5 µm in length; therefore, the shorter D2 is expected to exhibit a higher low bias current as demonstrated in Fig. 3

S4. Proposed Truth Tables and Symbols for AND-AND and AND-OR Logic Gates
Truth tables (A and B) and their proposed symbols (C-D) for electrical-optical hybrid three-input AND and AND-OR logic gates (see text).