Sensor design optimization of innovative low-power, large area MAPS for HEP and applied science

Fully Depleted Monolithic Active Pixels (FD-MAPS) represent a state-of-the-art detector technology and profit from a low material budget and cost for high energy physics experiments and other fields of research like medical imaging and astro-particle physics. Compared to the MAPS currently in use, fully depleted pixel sensors have the advantage of charge collection by drift, which enables a fast and uniform response overall the pixel matrix. The functionality of these devices has been shown in previous proof-of-concept productions. In this article we describe the optimization of the test pixel designs, that will be implemented in the first engineering run of the demonstrator chip of the ARCADIA project. These optimization procedures include radiation damage models, that have been employed in Technology Computer Aided Design simulations to predict the sensors behavior in different working environments.


INTRODUCTION
Silicon pixel detectors generally consist of a matrix of sensing diodes connected to readout electronics. Currently, there are two major types of technology used to implement this class of devices. First, hybrid detectors, that have the electronics integrated readout circuit on a separate die from the sensing active silicon substrate. In these devices each pixel is connected via bump bonding to the readout circuitry [1]. Secondly, monolithic detectors, that have the electronics integrated in the same Si substrate according to three main technological realizations; in (semi-monolithic) Depleted Field Effect Transistors (DEPFET) pixels [2,3], Silicon-On-Insulator (SOI) active pixels [4] and CMOS monolithic active pixels [5,6]. The DEPFET pixel technology offers very low-noise characteristics due to the small capacitance of the collection node. It is used in the Belle II experiment [7] as well as light source facilities, and astronomy [8]. The limitation of this technology lies in the necessary discharge of the collected electrons below the collection node, which requires a comparatively low occupancy and low radiation environments, and the necessity of additional external circuits for control and readout. The SOI sensors use a thin low-resistivity Si layer for the circuit implementation and high-resistivity bottom wafer. These two layers are separated by a buried oxide layer, with 50 µm thickness, in Fig. 1 (b). The collection electrode is biased at +0.8 V and the reverse bias voltage is applied from the back side of the pixel. Three different substrate thicknesses of 50,100, and 300 µm are simulated, using the same doping profiles provided by the foundry. This basic simulation setup has been previously validated with a production series, under the SEED project [17].
All simulations, if not stated otherwise in the figures, are performed at 300 K. The simulations neglect the nwell regions used in the implementation of PMOS transistors, assuming that the electrical characteristic and the radiation detection is not significantly affected. Due to the wide range of planned applications, these studies include a detailed analysis of the impact of different radiation levels on the pixel characteristics using radiation damage models for both the silicon bulk and the Si-SiO 2 interface. The adopted models, as well as the simulation results, are discussed in Sec. 2.2.

Electrical characterization
An example of the capacitance-voltage (CV) and current-voltage (IV) curves of a 50×50 µm 2 pixel is shown in Fig. 2 (b). The CV characteristics are, if not stated differently, simulated in AC with a frequency of 10 kHz. The black curve in Fig. 2 (b) represents the current measured at the collection diode and has been obtained from a two half-pixel domain, shown in Fig. 2 (a), with a 10 mV voltage difference applied at the top electrodes. In this way, a non-negligible current is flowing between the pixels if the substrate is not fully depleted. The red and blue curves correspond to current measured at the top pwell, and capacitance measured at the collection electrode in single pixel simulations, respectively. The dotted and dashed lines highlight the depletion voltage and onset of the punch-through currents, respectively. Both IV curves feature the point of sign change from negative to positive current values in form of dips in their absolute spectrum. These are defined as the voltage needed for full depletion V dpl and onset of the punch-through currents V pt , and correspond to the moment in which the single pixels become isolated from each other through the depletion region, and the moment in which the exponential increase of hole current between the pwell implantations and the back side p + contact starts. The sensors can be biased at a voltage higher than V pt , as long as the power consumption is not too large. Therefore, it is useful to extract the maximum allowed bias voltage at which a power consumption of 0.1 mW/cm 2 is reached. This voltage is marked as dotted red line, and will be referred to as V pw in the following. As it is visible in Fig. 2 (b), comparing the black dotted line and blue curve, the depletion voltage of these devices does not necessarily correspond to the voltage at which the minimum capacitance is reached. Due to the low doped epitaxial layer, full depletion of the substrate including the epi-layer, is only achieved at much higher voltages.
In the following analysis, capacitances and leakage currents are extracted at V pt , which we have chosen as an optimal and safe operating point. thickness. The black curve shows the absolute current measured at the collection electrode, the red curve corresponds to the current measured at the pwell on the top side of the sensor. The blue curve shows the capacitance of the full structure over the applied bias voltage range. The dotted black, dashed red, and dotted red lines mark the voltages of depletion V dpl , onset of the punch-through current V pt , and reached maximum power consumption V pw , respectively.

Prediction of radiation tolerance
The ARCADIA sensors are designed for a wide range of applications, which include HEP collider experiments. Future collider experiments like the FCC, require good timing performance and (partially) high radiation tolerance, especially for the central tracking and vertex detectors [18,19]. Ionizing radiation not only damages the surface of the sensor, which produces oxide charges at the interface between the Si and SiO 2 surface, but creates cluster and point-like defects in the silicon crystal lattice. These defects result in new energy levels within the band-gap and can function as traps which get electrically active when occupied, thus changing the electrical properties of the sensors, such as the depletion voltage (effective doping concentration) and the leakage (or dark) current. For a most realistic prediction of the impact of these defects, we have modeled both damage types, following the so called new Perugia model [20,21]. This three-trap model introduces two acceptor and one donor state in the bandgap for the description of non-ionising radiation damage in the silicon bulk. In addition, two trap states at the Si-SiO 2 interface are introduced to describe the effects of ionising energy losses, together with fixed oxide charges which build up due to trapped charges in the SiO 2 layer. While this model has been tuned and validated on p-type silicon, it has shown good performance for sensors produced by different vendors [20]. These results make us confident that the model has a good qualitative predictive power also for the ARCADIA sensors. However, a variation in absolute values of leakage current and capacitance can be expected due to varying impurity concentrations in the substrate.

Surface damage
To estimate the impact of surface damage on the sensor properties, we have employed a SiO 2 layer that features positive oxide charges. The concentration of these charges increases with the modeled total ionizing dose (TID), along with defect levels in the band gap. We are following the model introduced and summarized in [21]. The trap and oxide charge concentrations are plotted as a function of the 1 MeV neutron equivalent fluence and the dose in Fig. 3. Here, the fluence dose relation is used for 24 GeV protons of the CERN Proton Synchrotron with a proton hardness factor of 0.6 and a damage factor of D/φ = 3.3 × 10 −8 rad/(proton/cm 2 ) [22]. Because most potential applications of the ARCADIA technology do not expect doses greater than 10 krad, this value has been chosen as a reference for capacitance and leakage current estimates.  Table 1.
The impact of the SiO 2 and of the induced positive oxide charges is visible in the CV curves, as presented in Fig. 4 (a) of the example of a 50×50 µm 2 pixel. An increase of the capacitance is observed over the full voltage range (from 0 to -50V). This effect is present for all the pixel pitches. The CV curve without the SiO 2 layer is represented by the black line and shows the smallest values. When the SiO 2 layer is included, with a minimal concentration of positive oxide charge and traps, an increase of about 3 fF at the depletion voltage (-6.5 V) is observed. With increasing dose, of up to 5 Grad (50 MGy), the capacitance more than doubles. The first increase of the capacitance at the depletion voltage C end (V dpl ) for low doses (<1 Mrad), a second increase after 1 Mrad, and a saturation above 100 Mrad is shown in Fig. 4 (b). The two steps can be directly correlated to the positive oxide charge, and trap concentrations at the Si-SiO 2 interface, as shown in red dashed and dotted lines, respectively. The main impact of the increased trap concentration is a higher surface recombination velocity, while the positive oxide charges attract free electrons from the n-type epi layer and create an effective extension of the collection electrode. This effect is schematically visualized in the top plot of Fig. 5 (a), and its impact on the electrostatic potential and the electric field lines is shown in Fig. 5 (b). The strength of this effect depends on the sizes of the collection electrode and of the implant-free gap size between the diode and the pwell of the pixel. This allows for an optimization of the geometry and will be further discussed in Sec. 3.1.

Bulk damage
To simulate the pixels' electrical characteristics after irradiation with hadrons, we have employed a three trap model, similarly to [23,24]. The main properties like the activation energy, and the capture/emission cross-sections for electrons and holes of the defect levels are summarized in Table 1.
The concentration of these traps increases linearly with the fluence, as shown in Fig. 3, and this results in a linear increase of the leakage current. This effect is shown in Fig. 6, together with the comparison of a simple scaling of the current from low (T 1 = 248 K) to higher (T 2 = 300 K) temperatures, following [25]: with E g,ef f = 1.214 eV. Fig. 6 shows the measured leakage current at V pt as a function of the fluence φ neq for 50×50 µm 2 pixels in 50 µm thickness. The first observation is, that the induced surface damage has no significant impact on the leakage current, which is dominated by the volume generation currents induced by the bulk defects. The second observation is made using Equation 1 to scale the values measured at 248 K up to room temperature (shown in dotted lines). Since the model parameters are fitted to measurements at 248 K, it has to be mentioned that we observe a difference between the simulation results at 300 K and the scaling from 248 K, of a factor three.  Table 1. Properties for the two surface and three bulk traps [21]; listed as in which material they are introduced, how they are named in Fig. 3, which energy level in the Si bandgap they occupy, and their electron σ e and hole σ h capture cross-sections, respectively. Evaluating the operating voltages as a function of the fluence (see Fig. 7) a drop in the depletion voltage is visible for fluences > 1 × 10 13 cm −2 . This is consistent with a change of the effective doping concentration within the Si bulk, due to the introduced trap levels. The added acceptor levels first neutralize the n-type doping of the bulk and, with increasing concentration, invert the doping to p-type. Consequently, the p-n junction is moved from the back side to the border of the epi layer and the bulk to the front side of the sensor. In conventional Si diodes, the depletion voltage is expected to increase after the inversion of the effective doping of the silicon bulk [26]. However, for these pixel sensors, the depletion voltage is defined as the reverse voltage at which neighboring pixels become isolated by a depletion region, which corresponds to full bulk depletion before irradiation. But as soon as the bulk is type-inverted, the depletion region starts to grow from the front side between the epi layer and the bulk; therefore already with the small applied voltage of 0.8 V at the collection electrode, the electrodes of the pixels become isolated without any reverse bias applied. The type-inversion of the sensors above fluences of 1 × 10 14 cm −2 can be confirmed comparing transient simulations of Minimum Ionizing Particles (MIPs) using the HeavyIonModel of TCAD [27]. This model allows to simulate the charge deposition along a track within the sensor, defining the amount of generated charge as a function of the path length by the linear energy transfer (LET). Complementary GEANT4 simulations have been used to confirm the average charge deposition of MIPs of ∼ 80 e/h pairs or 1.28 × 10 −5 pC per µm. The charge deposition is instantaneously introduced after 10 ps, and the resulting transient signal is shown in the top plot of Fig. 8 (a) for a MIP incident in the pixel center, along a perfectly perpendicular trajectory, for fluences from zero up to 1 × 10 15 cm −2 . The transients have been simulated at V bias = −30 V, thus well above the depletion voltage over the full fluence range, and the time necessary to reach 95 and 99 % charge collection efficiency (t 95 and t 99 ), respectively, are reported in the plot on the bottom. In order to avoid inaccuracies of the simulation that impact the results, these times are defined as: At low fluences < 5 × 10 13 cm −2 the pulse shapes present a fast component due to the quickly collected electrons near the collection electrode, and a second peak due to the strong electric field at the pn junction on the back side of the sensor, which results in a higher drift speed of the charges generated close to the back side compares to charged originating at the pixel center. The electric field at V bias = −30 V is shown in the top plot of Fig. 8 (b) at different fluences. After moderate irradiation of up to 1 × 10 14 cm −2 , the electric field at the front becomes weaker, and the electrons get trapped by the increasing concentration of acceptor levels. For the highest fluences, a critical amount of the acceptors gets ionized and thus contributes to the space charge, as shown in the bottom plot in Fig. 8 (b). The space charge becomes negative below the electrode, where the electron density is highest, which results in a double peak in the electric field [28]. Additionally, the total collected charge significantly decreases at these extreme fluences due to the high concentration of donor as well as acceptor traps. The hole contribution to the signal seems to vanish completely after a fluence of φ neq = 1 × 10 15 cm −2 and the total collected charge lies below 20 %. The occupation of traps is dependent on the amount of available free charge carriers, as well as on the leakage current, the applied bias voltage, and the capture cross-sections. This results e.g. in a stronger double junction at higher temperatures due to easier occupation of the traps and higher leakage currents.
Since the employed trap model has been fit to data at 248 K [21], we report here only the results at 248 K. It should be mentioned that the amount and the type of radiation induced bulk defects depends on the particle type as well as on the particle energy of the irradiation [29]. In addition, the original impurities within the Si, like oxygen, can support or prevent the creation of certain defects [30,31].

DESIGN OPTIMIZATIONS
The pixel design optimization targets a small pixel capacitance to ensure low electronics noise, thus maximum signal to noise ratio, and high charge collection efficiencies within smallest possible time windows in order to decrease dead-times for high particle rates. To choose only a few geometries for each pixel pitch (10 µm, 25 µm, and 50 µm) with optimal performance, a large range of simulations with different electrode and pwell sizes has been performed. The results of this simulation campaign are summarized in the following in three different categories, focussing 1) on the pixel capacitance (Sec  The blue curves refer to simulations run at a temperature of 248 K, while the red curves refer to a temperature of 300 K.

Minimizing the pixel capacitance
The pixel capacitance can be lowered by decreasing the size of the collection electrode. However, due to the impact of the positive oxide charges within the gap between the electrode and the pwell, the gap size plays a major role and both quantities have to be analyzed in parallel. In the following, bulk damage is not considered in the comparisons between pixel designs, due to a negligible impact on the pixels' capacitance. An example of the importance of the gap size is visible in Fig. 9 (a). The capacitance is shown as a function of the dose for small, medium, and large electrode sizes with default and optimized gap sizes. Here the dose range has been limited to (0 -100) krad, which covers the expected doses reached after a few years of operation within a medical scanner used for proton CT. Comparing the small electrode with the default gap size shows, without the recognition of the SiO 2 layer and without positive oxide charges, a smaller capacitance than the medium electrode with optimized gap size. However, as soon as oxide charges are introduced, the trend turns around and the capacitance of the medium electrode stays ∼30 % lower than the capacitance of the non-optimized small electrode. While Fig. 9 (a) only shows the results for the 50 µm thick sensor, the same effect and very comparable absolute values have been found for thicker substrates. The capacitance for three different electrode sizes is shown as a function of the gap size for 50×50 µm 2 pixels in Fig. 9 (b). Due to boundary conditions, the pwell has a minimum size to facilitate the integration of transistors for the electronics; hence the gap size range is limited and most restricted for the largest electrode. For the 50×50 µm 2 pixel, we find a minimum capacitance for all electrode sizes at ∼ 2.5 µm gap size, for simulations that include the SiO 2 layer. In case of the large electrode size, it can be clearly seen that the capacitance decreases with increasing gap size, which corresponds to a smaller pwell size.

Operating bias voltage
The pixel designs for the different pitches impact these parameters due to changes in the electrostatic potential. Since the pixel design for the 25 µm pitch of the ARCADIA main demonstrator chip is fixed, its operating parameters are used as reference to allow the operation of different pixel flavors on the test-structure. Figure 10 shows the bias voltages (V dpl , V pt , and V pw ) for the three different thicknesses of the 10×10 µm 2 pixels (a), and 50×50 µm 2 pixels (b). The red shaded area marks the V pt ±10% of the reference 25×25 µm 2 pixels. While the reference voltage lies nicely within the limits of all 50×50 µm 2 pixel designs, the minimum bias voltage of the 10×10 µm 2 pixels varies strongly for the different designs. Only one design, with a large pwell, can be considered operational (depleted) at the reference voltage. The large difference in the operating bias voltage for the 10×10 µm 2 pixels has been an important observation and led to the conclusion that the test-structures with these pitches will be separated from the others in the final layout. This will ensure that a sufficient bias voltage can be applied from the front and  . Bias voltage at depletion V dpl (small dots), at the onset of the punch-through currents V pt (large dots) and at the point of maximum power consumption V pw (stars), for 10×10 µm 2 pixels (a) and 50×50 µm 2 pixels (b). The red shaded area corresponds to the V pt ± 10% of the reference 25×25 µm 2 pixel.

Uniform response
Transient simulations of MIP like tracks have been used to evaluate the charge collection and response across the pixels. To evaluate the signals usually the best and worst case scenarios are studied, which correspond to a traversing particle at the center and the corner of the pixel. For the comparison of different pixel designs, the time to collect 95 % and 99 % of the generated charges has been used. While charge losses due to radiation damage in the silicon crystal are not expected to vary between the pixel designs but rather with the substrate thickness, the study of response uniformity is neglecting bulk damage. The impact of surface damage on the signal formation has been tested in transient simulations, and has been found to be negligible. A general observation of the necessary time to collect 99 % of all charges in the pixel corner is the strong dependence on the pwell width (Fig. 11). Additionally, a large collection electrode size improves the collection of the charges from the corners of the pixels. However, the electric field strength below the collection electrode decreases with an increased collection node, which results in a slightly slower collection in the pixel center. Considering a homogeneous distribution of particles across the full area of the chip, motivates an optimization for uniformity rather than peak performance in localized areas. Figure 11. Time required for 99 % charge collection in the center (blue) and corner (green) of 50×50 µm 2 pixels with medium sized nwell, as a function of the pwell over pitch ratio. The results are shown for three different sensors thicknesses.
These considerations lead to a choice of 25×25 µm 2 and 50×50 µm 2 pixels, with minimum pwell and maximal electrode size. Due to the small pitch, the 10×10 µm 2 pixels are much less effected by slow charge collections in the pixels corners. Instead charge sharing is much more pronounced and the larger concern lies in the so-called channel choking, which describes the effect of a potential barrier occurring when the sensing window becomes too small in comparison to the pwell size. To overcome this problem, a design that features the electronics in islands of deep pwells within the pixel corners, has been studied and a picture of a 2 × 2 pixel matrix is shown in Fig. 12 (a). With this approach, a large enough (deep) pwell size can be achieved to allow for the integration of the electronics without the risk of a non-functional diode. The resulting charge collection efficiencies for a range of (deep) pwell sizes, given here in half-sizes, are presented in Fig. 12 (b) at t = 5 ns for particles incident along the diagonal of the 2 × 2 pixel matrix. The first observation is that for deep pwell size < 3 µm, the charge collection after 5 ns is always above 99 %. The second observation is that even with a deep pwell size of 3 µm, the charge collection still reaches 90 % after 5 ns. This feature of fast and uniform responses motivates further studies towards the integration of fast monolithic pixel designs for applications that require fast timing capabilities.

CONCLUSIONS
The first engineering run of the ARCADIA main demonstrator is currently in production. The preparations have been accompanied with a large simulation campaign to study possible improvements of the pixel designs in order to decrease the pixel capacitance, and optimize the charge collection. This campaign included first tests of radiation tolerance, using the latest radiation damage models, and has investigated in detail the impact of surface charges on the electrical properties. The capacitance of the selected designs is summarized in Fig. 13 (a), and is shown before and after a dose of 10 krad is applied. Without surface damage, all pixels feature a single pixel capacitance < 3 fF. The charge collection efficiencies for the fastest designs are shown in Fig. 13 (b), for central (straight) and corner (dashed) hits. The times for 99 % CC are summarized in Table 2.
These studies led to the choice of a few different designs of pixels with 10/25/50 µm pitch that will be realized in a number of test-structures, such as e.g. matrices of 1 × 1 and 2 × 2 mm 2 . These structures will   Table 2. Times for 99 % charge collection for MIP-like charge depositions at the center and the corner for pixels with three different pitches, given for three substrate thicknesses (50/100/300) µm.
allow a validation of the physics models used in the simulation and will be characterized using, besides basic IV and CV measurements, radioactive sources and a laser for e/h pair generation.