The physical model of the HP memristor is shown in Figure 1. It is composed of two layers of titanium dioxide (TiO₂) film sandwiched between two metal platinum electrodes.

Based on the definition in literature [3], the resistance value of the HP memristor, M(t), is defined as M ( t ) = M O F F + ( M O N − M O F F ) ω ( t ) D (1) where ω(t) is the thickness of the current doped layer and D is the total thickness of the two TiO₂ films. M O F F and M O N are the memristance limits when ω(t) = 0 and ω(t) = D, namely, the maximum resistance value and the minimum resistance value. Substituting x ( t ) = ω ( t ) / D into Eqs 1, 2 is derived: M ( t ) = M O F F + ( M O N − M O F F ) x ( t ) . (2)

For an ideal memristor model, its ion drift model is d x d t = η v M O N D 2 i ( t ) , (3) where η v is the constant of memristor ion mobility in the uniform field, η v ≈ 10 − 14 m 2 ⋅ s − 1 ⋅ V − 1 , i(t) is the current traveling the memristor.

Since the physical memristor is a nanometer-sized circuit component, the memristor can generate a huge electric field when applying a tiny voltage. Therefore, the ion movement inside the memristor owns significant non-linear characteristics. Therefore, when Eq. 3 is multiplied by the non-linear window function, Eq. 3 is rewritten as d x d t = η v M O N D 2 i ( t ) f ( x ) , (4) where f(x) is the window function.

The window function used in this paper is [4] f ( x ) = 1 − ( 1 − 2 x ) 2 p , (5) where p is a positive integer and p is used to describe the degree of non-linearity. This paper selects p = 1 as the window function for obvious non-linearity analysis.

Mathematical models of controlled memristor mainly include two kinds. One is a charge-controlled memristor, and the other is a magnetic flux-controlled memristor. This paper mainly introduces charge-controlled linear memristor and non-linear memristor.

According to the equation Q ( t ) = ∫ 0 t i ( t ) d t (Q is the quantity of electric charge), integrating the time on both sides of Eq. 3, and substituting it into Eq. 2, then the mathematical model of the charge-controlled linear memristor is obtained in Eq. 6: M ( t ) = M ( 0 ) + k 1 Q ( t ) k 1 = η v M O N ( M O N − M O F F ) D 2 , (6) where M (0) is the initial memristance which is M ( 0 ) = M O F F + ( M O N − M O F F ) x ( 0 ) .

According to the equation Q ( t ) = ∫ 0 t i ( t ) d t , integrating the time on both sides of Eq. 4, and substituting it into Eq. 2, then the mathematical model of the charge-controlled non-linear memristor is obtained in Eq. 7: M ( t ) = M ( 0 ) + Δ M ( 1 1 + e 4 k 2 Q ( t ) − 1 2 ) k 2 = η v M O N D 2 , (7) where Δ M = M O F F − M O N .

This section will use MATLAB to simulate characteristics of the two types of memristors mentioned in the above section. The parameters of the two types of memristors are listed as follows: M O N = 100 Ω , M O F F = 20 K Ω , D = 10 n m , η v = 10 − 14 m 2 ⋅ s − 1 ⋅ V − 1 . (8)

Figure 2 shows the relationship between the memristance changes and the amount of charge or flux for different types of linear and non-linear memristor models. The characteristic curve of the non-linear memristor tends to the physical experiment result provided in [12] which shows that the mathematical model of the non-linear memristor is reasonable.

Figure 3 shows that the non-linear charge-controlled memristor model also has a hysteresis effect. Furthermore, both models demonstrate the typical current-voltage hysteresis loop of the memristor with i = 2 × 10⁻⁴sin(2πt).

This paper designs a dual-mode memristor bridge circuit as shown in Figure 4.

In Figure 4, the dual-mode switching is realized by a single-pole double-throw switch S ₁. Switch S ₁ has two interfaces K ₁ and K ₂ and a pulse conversion control signal interface. The control signal interface is imposed by signal P _A which makes S ₁ switch between K ₁ and K ₂ for control and output modes. The positive and negative pulses are generated by switching through single-pole double-throw switches S ₂ and S ₃ and single-pole single-throw switch S ₄. Switch S ₂ has two interfaces K ₃, K ₄, and switch S ₃ has two interfaces K ₅, K ₆; the two-pulse conversion control signal interface is imposed by signals P _B and P _C , respectively. The single-pole single-throw switch S ₄ has a pulse conversion control signal interface imposed by the pulse control signal P _D . The portion of the circuit for obtaining the output voltage is composed of MOS transistors T ₁ and T ₂. The turn-on voltages of the MOS transistors T ₁ and T ₂ are both V _T , and the gate voltages of the two transistors are both V ₁. In the control phase, in order to obtain the zero output voltage, let V ₁<V _T . Otherwise, in the output phase, let V ₁>V _T . The conditions of switches in the two modes are shown in Table 1.

There are two modes of dual-mode memristor bridge synaptic circuit, control mode, and output mode. The control mode is to make the non-linear memristor reach the required memristance faster so that the memristor can obtain the required synapse weights. The output mode is to obtain the required output with the minimum influence on the memristor’s change. The dual-mode memristor bridge synapse circuit is an improvement of the type I memristive bridge circuit as shown in Figure 5.

As shown in Figure 4, in the control mode, the equations for calculating the memristances of M ₁-M ₄ in the control phase are listed as follows: M 1 = M 01 + Δ M ( 1 1 + e 4 k 2 − v i n g M 1 + M 2 t v − 1 2 ) , (9) M 2 = M 02 + Δ M ( 1 1 + e 4 k 2 v i n g M 1 + M 2 t v − 1 2 ) (10) M 3 = M 03 + Δ M ( 1 1 + e 4 k 2 v i n g M 3 + M 4 t v − 1 2 ) , (11) M 4 = M 04 + Δ M ( 1 1 + e 4 k 2 − v i n g M 3 + M 4 t v − 1 2 ) , (12)

In the output mode, when the input voltage is V _inN, the output voltage equation of the dual-mode memristor bridge synaptic circuit as shown in Figure 4 is derived as Eq. 13 according to the voltage division Eqs 14, 15: V out = V A − V B = ( M 2 M 1 + M 2 − M 4 M 3 + M 4 ) V i n N , (13) V M 2 = M 2 M 1 + M 2 V i n N = V A , (14) V M 4 = M 4 M 3 + M 4 V i n N = V B . (15)

Let ω = M 2 M 1 + M 2 − M 4 M 3 + M 4 = M 2 M 3 − M 4 M 1 ( M 1 + M 2 ) ( M 3 + M 4 ) ; then, V o u t = { ω × V i n N ,                   V 1 > V T 0 ,                                                 V 1 < V T    , (16) where ω satisfies V o u t = { negative   ,                       M 2 M 3 < M 4 M 1 0   ,                                                       M 2 M 3 = M 4 M 1     positive   ,                           M 2 M 3 > M 4 M 1 .

According to Eqs 9–12, we can know there are two methods to make the synaptic weight change more linear for the non-linear memristor. One is to increase the duration of t _v with the input V _in unchanged. The other is to change the input V _in and keep the duration of t _v unchanged. Because of the timeliness requirement of the synapse circuit, the paper employs the method by varying the input V _in in the control mode.

In order to obtain the more accurate models, this paper uses the simulated annealing method random search algorithm to select a suitable input V _in because of its simple structure and the fast search speed.

When the input V _int is sampled in a sufficiently small interval, T _s , by dividing the duration of t _T . Then, the simulated annealing method can be used to obtain a more accurate input voltage V _int . This method is applied to the memristive bridge synapse circuit as shown in Figure 4.

The detailed specific steps are listed as follows.

Step 1: Set the initial input voltage V _int , temperature T, end temperature T _z , the maximum number of iterations L for each temperature T, the interval time T _s and the maximum value of the input voltage that is changed at each moment through measurement. The input voltage is selected at each moment between the initial input voltage and the maximum voltage.

Step 2: T = jT, j is the descent rate and j∈(0, 1), n is the number of iterations. To obtain the evaluation function for each iteration, E t T ( n ) = M linear t T − M non - linear t T , for each memristance under the current input voltage; that is, the valuation function is the memristance difference between the linear memristor and the non-linear memristor at time t _T .

Step 3: Select a new input voltage V _in at time t _T randomly within the set voltage range. Then, calculate the memristances and evaluation function of the non-linear memristor E t T ( n + 1 ) = M linea r t T − M non-linea r t T .

Step 4: If E t T ( n + 1 ) > 0 , then Δ E t T = E t T ( n + 1 ) − E t T ( n ) ; otherwise, n = n+1, and return to Step 3.

Step 5: If Δ E t T <0, accept the changed input voltage; otherwise, judge whether to accept this voltage according to the probability e − Δ E t T T . Let n = n+1.

Step 6: If Δ E t T < − 10 5 , terminate the algorithm.

Step 7: If n < L, return to Step 3.

Step 8: If T < T _z , terminate the algorithm; otherwise return to Step 2.

According to the above steps, the same parameters of memristors are set for the non-linear memristor and the linear memristor bridge synapse circuits as shown in Eq. 8.

As shown in Figure 6, when the simulated annealing method selects an accurate input voltage, the memristance M ₁ coming from the non-linear memristive bridge synapse circuit can be significantly linearized.

It can be seen from Figure 7 that the output voltage of the non-linear memristor bridge synapse circuit is not linear by using improved simulated annealing method, and the absolute values of output voltages are much greater than those of the linear memristor bridge synapse circuit as the time goes further because of non-linearity of the input voltage.

As mentioned above, when an input voltage or current works on the memristor, the memristance will change. However, if positive and negative pulses are applied on the memristor, the effect of input voltage applied on memristance can be reduced according to the memristance measurement method mentioned in [19]. Therefore, the output mode must be able to automatically switch the voltage direction as shown in Figure 4. As illustrated in Table 1 and Figure 4, in the positive pulses, the current flows from C to D, and the output voltage is obtained. In the negative pulse, the current flows from D to C, which is opposite to the current flow of the positive pulse, and no voltage is outputted.

According to Eqs 8–16, the output voltage changes for models are obtained and shown in Figure 8.

As shown in Figure 8, the red line represents the output voltage for the non-linearity because only the control mode works. If the output mode is added, the line of output voltages becomes more linear as shown in the orange line. This simulation verifies that the dual-mode memristor synapse circuit can realize that both synapse weights and the output voltages can be linearized. The speed of obtaining weights can be accelerated by using the proposed method mentioned in this paper.

Based on the analyses in the previous section, dual-mode memristive bridge synapses can more efficiently simulate weights which can be applied to image processing template operators in cellular neural networks. The cellular neural network uses different template operators to transform the input image into the desired output image. Therefore, the synaptic circuit mentioned in the previous section can be used to construct a new type of memristive bridge neural network, which can be employed in image processing. Since the input of the traditional memristive bridge neural network is a fixed value, the memristor exhibits non-linearity which forms the template slowly, and the synapse weight difference is big. Therefore, the dual-mode memristive synaptic neural network can shape the template faster with higher accuracy compared to the traditional memristive bridge neural network.

As shown in Figure 9, the circuit is mainly divided into three parts such as dual-mode memristive bridge synaptic circuit, differential pair circuit, and effective load circuit.

1) Dual-mode memristive bridge synaptic circuit

As shown in Figure 9A, this synapse circuit in the control mode changes the input voltage to make the synapse weight change like a linear trend. In the output mode, by generating symmetrical positive and negative pulses, the synaptic weight of the memristive synapse circuit is minimally affected, and the expected template operator can be obtained faster. The entire neural network is composed of multiple dual-mode memristive bridge synaptic circuits, and the synaptic circuits are independent of each other.

2) Differential pair circuit

As shown in Figure 9B, the differential circuit is located on the right side of the dual-mode memristive bridge synapse circuit, which is a differential amplifier composed of transistors. The corresponding function is to convert the output voltage of the dual-mode memristive bridge synapse circuit into current.

3) Effective load circuit

As shown in Figure 9C, the effective load circuit is located on the right side of the differential pair circuit. It is connected in series with each dual-mode memristive bridge synaptic circuit. This circuit coverts the current coming from the differential pair circuit into the voltage signal through the resistive load.

In the field of bird repelling for airports, bird characteristics recognition requires edge extraction from bird images. This paper combines a dual-mode memristive bridge synaptic neural network with a cellular neural network template to realize the edge extraction of these pictures. The commonly used cellular neural network template is 3 × 3, so this paper uses the synaptic neural network with nine dual-mode memristive bridges as shown in Figure 9 to implement. In each circuit, the corresponding output value can be obtained by inputting different pulse signals.

The template based on edge extraction includes A = [ 0 0 0 0 4 0 0 0 0 ] , B = [ − 1 − 1 − 1 − 1 8 − 1 − 1 − 1 − 1 ] , I = 0.3.

The parameters of the memristor in Figure 9 are listed in Eq. 8. The parameters of MOS tube in Figure 9 is V _T = 3v.

The pixels of an image with M×N are inserted into a cellular neural network with a template size of 3 × 3; the pixels are iterated according to the following equation: v x i j ( n + 1 ) = ∑ c ( k , l ) ∈ P 1 ( i , j ) A ( i , j ; k , l ) v y k l ( n ) + ∑ c ( k , l ) ∈ P 1 ( i , j ) B ( i , j ; k , l ) v u k l ( n ) + I v y i j ( n ) = 1 2 ( | v x i j ( n ) + 1 | − | v x i j ( n ) − 1 | ) , where v _x is the state value, v _y is the output value, and v _u is the input value, 1 ≤ i ≤ M, 1 ≤ j ≤ N, P 1 ( i , j ) = { c ( k , l ) | max { | k − i | , | l − j | } ≤ 1,1 ≤ k ≤ M , 1 ≤ l ≤ N } .

When |v _x |>1, stop iteration and output v _y .

Figure 10A shows the results of edge extraction by using the non-linear memristive bridge synaptic circuit. The results of edge extraction of bird image are realized by using this template for the dual-mode memristive bridge synaptic neural network as shown in Figure 10B. The response speed of edge extraction is faster for the dual-mode memristive bridge synaptic neural network than that of the non-linear memristive circuit. The comparison of some indexes of the two methods is shown in Table 2.

As shown in Figure 10, the iteration times, t, for obtaining templates by using the proposed dual-mode memristive bridge synaptic neural network are between 30 and 40, while the iteration times for obtaining templates in using traditional non-linear memristive bridge synaptic neural network are between 40 and 50. It is obvious that the dual-mode memristive bridge synaptic neural network is faster than the traditional non-linear memristive bridge synaptic neural network for templates recognized.

In this paper, the performance index FOM (Figure Of Merit) will be used to quantitatively compare different edge extraction algorithms, where the FOM equation is listed as follows: FOM = 1 max ( Q i , Q t ) ∑ i = 1 Q t 1 1 + α d i 2 , where Q _i is the number of edge pixels of the original template. Q _t is the actual number of edge pixels detected. α is the compensation coefficient, α = 1/4, and d _i is the shortest distance between the detected edge point and edge point of the original template. FOM ∈ [0,1]; the larger the index FOM, the better the effect. The edge results of the bird image extracted by different methods are evaluated, and the FOM values are shown in Table 2.

According to Table 2, it can be seen that the FOM value obtained by the proposed method in this paper is larger than that of the traditional method, indicating that the edge extraction effect of the proposed method is better. The iteration times of the proposed method are also smaller than those of the traditional method. Therefore, compared to the traditional non-linear memristive bridge synaptic neural network, the dual-mode memristive bridge synaptic neural network has a more efficient performance in edge extraction.