Two-stage frequency compensation for Doppler shift on BPSK transceiver with LDPC codes for free-space optical communication systems

The deployment of low earth orbits is seen as a promising way of enlarging data capacities as well as high data rates. Catering to these interests, optical communication presents possible ways of larger bandwidth than microwave communication. The current generation of mainstream communication systems are classified as coherent systems and incoherent systems, and in particular, coherent systems have received more attention owing to their high receiving sensitivity. This study investigates a digital coherent transceiver, based on binary phase-shift keying technology. As coherent demodulation will be affected by considering the Doppler shift effect in digital demodulation, Doppler shift of ± GHz can be compensated by adopting a two-stage frequency offset compensation. Moreover, by leveraging a fast filtering algorithm a considerable amount of resource consumption is saved in its engineering implementation, and its sensitivity can be significantly enhanced via a high-speed parallel error-correction codec based on low-density parity-check technology.


Method
A coherent optical communication system is based on coherent detection and corresponding modulation mode. For coherent detection, the photodetector in the receiver is responsive to the light field generated by the superposition of local oscillator (LO) light and signal light. The system signal-to-noise ratio needs to be optimized by the spatial coherence between the stronger LO light and the received signals light, in order to enhancing the detection sensitivity of the system (as illustrated in Figure 1) [7]. The expressions of the time-domain signal for signal light and LO light are as follows [8]: where, E s and E LO denote the amplitude of signal light and LO light, ω s and ω LO depict the frequency of signal light and LO light, φ s and φ LO symbolize the initial phase of signal light and LO light, and ϕ(t) represents the modulation phase of BPSK.
Assuming that the transmission direction and polarization direction of signal light E s (t) and LO light E LO (t) are consistent, their frequencies are mixed to eliminate the direct current and unresponsive high-frequency component for other detectors, thereby retaining the responsive component of different frequencies for detectors featuring a frequency component of ω s − ω LO .Therefore, the current output of the photodetector is expressed as: where, R represents the responsivity of the photodetector, and P S and P LO denote the optical power of signal light and LO light, respectively. The aforementioned equation contains the overall information of signal light and LO light field. Herein, ω s − ω LO is constant, and the modulation information φ(t) is rendered in the output current with phase locking. For BPSK modulation, with a frequency difference of 0 and a carrier-phase difference locked at 0, the modulation phases of 0 and π correspond to the digit output of 1 and 0. For directly modulated on-off keying (OOK), the laser drive current is directly modulated using the electrical signal, So a variation of the output light with respect to the changing electrical signal have been rendered. The exact time for the generation of a signal photon via stimulated radiation of the laser source is unpredictable, and the radiant time of numerous photons is a Poisson stochastic process. The theoretical performance limit of an ideal OOK receiver can be calculated via the following equation, which serves as a foundation and reference for the performance of various receivers in other optical communication systems [9]. Frontiers in Physics frontiersin.org 02 As listed in Table 1, with the same bit error rate (BER), the required photon-bit number of BPSK light homodyne is evidently smaller, while those of direct detection and DPSK heterodyne demodulation are larger. Therefore, the coherent BPSK-based homodyne optical receiver serves as the optimal choice to enhance the receiving sensitivity of long-distance laser communication systems.

Doppler effect
Spatially coherent communication, which requires a stable frequency difference, cannot compensate the random changes in frequency difference so that the eventual coherent demodulation has been affected significantly which leading to a deterioration of the BER. In space, Doppler shift is generated by the relative motion between satellites with different orbits and between the satellite and earth [10][11][12]. Moreover, the phase error originating from the Doppler shift varies rapidly, which may reach the GHz-scale, thereby causing a variation in the phase difference. Presumably, the laser source moves at a relative velocity of v along V direction, while the angle between V and the propagation direction of the optical carrier is θ, as illustrated in Figure 2.
The frequency shift of the Doppler spectrum can be mathematically derived through Lorentz transformation [13]: where, β ] C , and c denotes the velocity of light. Particularly, the Doppler frequency shift is considerable and can vary rapidly. When an identical frequency exists, the frequency drift is induced by signal interference has a fast time-varying nature. Therefore, the Doppler frequency shift, in this case, will directly affect the received useful signal, and then impacting the receiving quality. In coherent systems, the LO and intermediate frequency (IF) of signals are actually processed, whereas as a desirable condition, IF should merely vary with different modulation modes under investigation. However, random IF shifts may occur due to the deleterious effects of various noises. The Doppler shift serves as the factor generating enormous IF shifts which enen as introducing considerable noise interference. This phenomenon can significantly impact the demodulation of coherent systems and eventually lead to a bad effect on BER, which jeopardizes the coherent performance and system stability. Therefore, compensation on Doppler shift is definitely required to ensure reliable communication.
With the advancement of digital signal processing (DSP), compensation techniques based on DSP for frequency and phase offset have been extensively investigated and developed [14][15][16][17], whose preemptive characteristic is that the system adopts open-loop compensation to compensate frequency and phase offset without using of an optical phase locked loop (OPLL). The compensation of Doppler shift in space has been performed in this study. In our works, Fast Fourier transform (FFT) frequency shift is used to estimate the wavelength of the LO laser so that the frequency offset of the carrier ring can be compensated which will solve the issue of Doppler shift in laser-based space communication systems.

Experimental setup
The following scheme was adopted for the experiment in this paper. The structure of BPSK-based coherent optical communication comprises three parts: the transmitter part, space-channel part, and the receiver part. As illustrated in Figure 3, the transmitter part of BPSK includes a 1.25 Gbps datasignal channel, a laser of band 1,550 with a line-width of 10 kHz, an electric-driven amplifier, and a Mach-Zehnder modulator (MZM). The digital signal is generated through a field-programmable gate array (FPGA), which subsequently transfers to the electric-driven amplifier after low-density parity-check (LDPC) encoding, data scrambling, framing, and other processing methods. Following amplification, the data is fed back to the MZM for electro-optical modulation, and the output optical signal is transmitted via the optical antenna. If the signal's optical power is attenuated due to long-distance transmission along the space channel, signals received by the optical antenna shall be amplified and filtered using an erbium-doped fiber amplifier (EDFA) and an optical filter before reaching to the receiver system. Subsequently, the received signal light and LO light are mixed by a 180°frequency mixer. Thereafter, the mixed optical signals are converted into electrical signals using a balanced detector, and electrical signals, as the output of the detector at this moment, are conveyed as radio-frequency signals after downconversion. Finally, the signals are sampled via a high-speed analogto-digital converter (ADC) and then processed using a digital processor.

FIGURE 2
Schematics of the Doppler effect.
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FIGURE 3
Schematics of BPSK transceiver integration. Considering the miniaturization and convenience of use, the FPGA is adopted to digitally perform high-speed parallel demodulation. As illustrated in Figure 4A, the entire processing procedures include carrier recovery, timing synchronization and self-adaptive equalization. The acquired digits after equalizing are baseband signals for the subsequent frame synchronization, data scrambling, and LDPC decoding. Subsequently, the bit error test is conducted on the decoded valid digits. The implementation of digital demodulation and LDPC are emphasized in the following sections.

Carrier recovery
Carrier recovery can be divided into two sections: carrier acquisition and carrier tracking. As illustrated in Figure 4B, twostage FFT frequency scanning is adopted for carrier acquisition to realize ± 625-MHz wide range frequency compensation. The intermediate frequency carrier is matched by the direct digital synthesizer (DDS) frequency. After frequency mixing and filtering, the frequency offset is calculated by reducing the signal sampling rate and Fourier transform. The point with the maximum FFT power corresponds to the frequency offset position. The compensation is realized by adjusting the local oscillator laser wavelength considering the wavelength adjustment error and compensation accuracy.
In the second stage, we adopt the same method to modify the above setting parameters so as to meet a ±100-MHz accuracy frequency offset compensation. Having estimated the coarse frequency offset induced by the Doppler shift and wavelength adjustment error, the DDS frequency is set as the estimated value, and the system enters the loop-tracking stage. As the acquisition module cannot determine the start time for reacquisition, the acquisition should be controlled using the frame synchronization module. The acquisition is conducted every second when the system is not in the frame-synchronization status.

Timing synchronization
The parallel-timing synchronizer is illustrated in Figure 4C, which is implemented by exploiting the Gardner synchronization algorithm. This strategy is used to extract the deviation between the transmitter clock and the asynchronous sampling clock for clock recovery, ensuring that the sampling data is maintained at the optimal sampling point. In the system, each channel possesses an independent numerically-controlled oscillator (NCO) and an interpolator. Here, Lagrangian interpolation is used to achieve a higher precision than oversampling. Error detection is performed after aligning the interpolation results, and the timing error is stabilized in a short time. The error is directly accumulated and is subsequently fed back to the loop filter. An additional consideration is that the timing error should match our loop filter for the best results. The loop filter is used to filter the highfrequency components and error signal smoothing. Additionally, it is adopted to adjust the NCO, whose output controls the interpolation position.

Self-adaptive equalization
The serial structure of a least mean square (LMS)-type selfadaptive equalizer is illustrated in Figure 4D. The parallel structure is similar to the serial structure, with the exception that the filter and the decision maker are switched to a parallel configuration. As no training sequence is set in the frame structure and the signal is continuous, the LMS equalizer does not perform training but directly decides the feedback to update the filter coefficients.
The signals entering the self-adaptive filter are signals with doubled symbol rate after timing. After the filtering process, the decision step is performed for every second point of signals, and the decision results are mapped as constellation points. Moreover, error signals are acquired by subtracting the constellation points from the decision results. By introducing error signals to the update equation, the filter coefficient is accordingly updated. After multiple decision-making, error acquisition, and coefficient updating, the filter coefficient will be stabilized at status with a small mean-square error.

LDPC error correction
The LDPC code features excellent characteristics, including approaching the Shannon limit, high convergence rate, and high bandwidth efficiency, which empowers the high-speed long-distance optical communication system by greatly enhancing its sensitivity. Considering the resource consumption and implementation, serialbit-flip (SBF) algorithm was employed in this experiment to enable the hard decision of LDPC. The overall structure of the encoder is illustrated in Figure 5A. Herein, S-ENCODER represents the serial encoder, whose structure is displayed in Figure 5B. The implemented structure of shift-register-adder-accumulator (SRAA) is demonstrated in Figure 5C. With a clock frequency of 125 MHz, the serial encoder of each channel can achieve a code throughput of 125 Mbps. The structure of parallel decoder is illustrated in Figure 6. It mainly includes input buffer, update buffer, output buffer, mode buffer, adder, multiplexer, matrix multiplier and comparator. The decoding result is obtained by computing the adjoint matrix through multiple iterations.

Simulation
Considering resource consumption and feasibility, the digital demodulation and error correction algorithm of this experiment was first simulated in MATLAB. We used a 1.6-GHz IF and 1.2497-Gbps symbol rate as the input RF data collected by the ADC to verify the implementation effect of carrier recovery and bit synchronization. The transmission symbols are square waves and have reached the maximum bandwidth. In this simulation design, the frequency offset, which is caused by different oscillator frequencies between the transmitter and receiver and by Doppler effects, is implemented via two-stage compensation. In the first stage, we estimate a rough large-frequency offset and then adjust the local oscillator laser wavelength in the actual system. Then, only the second stage and subsequent algorithms are implemented in the simulation. The floating-point simulation results are listed in Table 2, in which the total data sample size is 2 × 10 6 bits. The simulation results indicate that the method adopted in this experiment is close to the theoretical results. The receiving sensitivity after demodulation mainly depends on the signal-to-noise ratio (SNR) of the input signal. As long as the frequency offset is in the capture range, it has little impact on the bit error rate.

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In the simulation, when Eb/N0 = 10, the spectra and constellation diagrams of certain signals are illustrated in Figure 7. In the actual system, the constellation results can be used to evaluate the influence of signallevel characteristics, noise, and inter-symbol interference (ISI). The results of SBF algorithm after 20 iterations are illustrated in Figure 8. The SBF algorithm exhibits a BER lower than 10 -7 at 6.1 dB, while the undecoded approach renders a BER of 10 -7 at 11.3 dB. Therefore, with a BER of 10 -7 , the SBF algorithm demonstrates a gain of 5.2 dB. By adopting the same calculation approach, the gain is approximately 4.5 dB, with a BER of 10 -6 and approximately 3.5 dB with a BER of 10 -5 .

Resource analysis for implementation
In the stage of carrier recovery, the COordinate Rotation DIgital Computer (CORDIC) algorithm is adopted by the parallel DDS for implementation without requiring any hardware multiplier (DSP). The frequency mixer consists of two parts: I and Q, and each part has 32 parallel channels and 64 DSP in total. The FFA decomposition algorithm is used in the LPF, as illustrated in Figure 9. Two filters  Frontiers in Physics frontiersin.org with a length of N can be decomposed into 3 filters with a length of N/2, thereby decreasing the DSP cost from 4N to 3 N. Moreover, a 64-order FIR filter is adopted in practice with 32 parallel channels, which can be decomposed five times with the DSP quantity = × 64 × 32 × ( 3 4 ) 5 = 972. The complex multiplication prior to the FFT involves for DSPs. Therefore, the carrier recovery part requires 1,040 DSPs in total.
In the timing synchronization stage, linear interpolation is adopted using the interpolator with two DSPs in each channel and 64 DSPs for 32 channels in total. With a sampling rate of 10 Gbps and a symbol rate of 1.25 Gbps, 10/1.25 symbols exist for 32 points. Furthermore, by considering the boundary and time offset, the DSP cost of error estimation = ( 10 / 1.25 + 2) × 2 = 20. Accordingly, the DSP cost of timing synchronization is 84.
In the self-adaptive equalization stage, the equalization filter is a complex filter, as demonstrated in Figure 10. The implementation of one complex filter is equivalent to implementing four real filters. Signals from 2 × (10/1.25 + 2) = 20 parallel channels are input to the filter. As the processing is only concerned with the symbol rate for filtered signals, the output is reduced to 8 parallel channels. After simulation, the requirements can be fulfilled by adopting a 32-order filter. Initially, a 2-phase separation is performed using the 32-order  Frontiers in Physics frontiersin.org filter, thereby rendering two 16-order filters with 8 parallel channels.
Therefore, the number of DSPs required for digitally coherent demodulation is calculated as 1,040 + 84 + 668 = 1792. In this experiment, an FPGA obtained from Xilinx, Inc. (type: VU9P) was employed for design implementation. This resource could effectively fulfill the research demands.
In the LDPC part, the encoder comprises 10 serial encoders and 20 buffer RAM in total for the input and output operations. As the circulant submatrix in (8160, 7136), the LDPC has a dimension of 511, and each SRAA requires 511 lookup tables (LUTS) and 1,022 registers. The matrix generator requires approximately 150 LUTS, and a serial encoder requires approximately 1200 LUTS and one 18K-RAM. Moreover, 3000 LUTS are reserved for the parallel-to-serial conversion and control circuit of the encoder. With a working clock frequency of 125 MHz, the total resource requirements of the encoder comprise 30,000 LUTS and 60 18-RAMs. Additionally, the decoder stage involves 511 parallel decoders comprising multiplier, adder, pattern transformer, comparator, and RAM. According to statistics, with a clock of 125 MHz, 50,240 LUTS and 35 18k-RAMs are required.

Discussion
The receiving sensitivity is an essential indicator of the performance of the free-space optical receiver. At the receiving end, the received input-light power is monitored by a 50:50 beam splitter, and bit error tests are conducted simultaneously. By manipulating the attenuated energy of the attenuator, the input light power at the receiving end is varied from −52 to −47 dBm, then  we test the receiver performance sequentially. A BPSK constellation diagram obtained via demodulation without encoding and a sensitivity of −40 dBm is illustrated in Figure 11A. It can be seen that the noise introduced by the low-noise optical amplifier and the balance detector cause a large EVM value after demodulation (the data distribution is not concentrated in the white circle in the figure).
The eye map distribution after demodulation, which is a communication performance evaluation method, is illustrated in Figure 11B. In the figure, a thicker eyelid of eye diagram can be obviously found, which is due to the distortion of the maximum signal at the sampling time. Moreover, the over-zero point at the intersection of the two oblique lines can express the characteristics of  Frontiers in Physics frontiersin.org 09 the signal response in the time domain, indicating whether the upward and descending time of the signal is symmetric and whether the duty cycle is 50%. In this experiment, the final demodulation signal was slightly distorted by the detector and the limited bandwidth of the ADC sampling chip.
Bit error tests are conducted on the original pseudorandom binary sequence data before encoding and the encoded data. Figure 11 depicts the bit error test results. With a BER of 10 −7 as the benchmark, the receiving sensitivity without LDPC encoding attained a value of −49 dB, while the BER reached −52 dBm after LDPC encoding. Notably, compared to the theoretical limit, only a loss of −4 dBm occurs as 56 dBm.Compared with the similar experiment work recently we know [18], our current test results are about 1 dB better than them. In terms of the coding gain, the simulation results demonstrated that by employing the SBF algorithm, when the BER magnitude was in the scale of 10-7 , the coding gain in the actual experiment was 3.5 dB (the theoretical gain is close to 5 dB), for which the error might be attributed to issues involving the actual system's SNR and baseband signal quality after recovery. In our system, the sensitivity gap is mainly attributed to the noise factor of 4.5 dB introduced by the optical preamplifier, as the theoretical value is 3 dB. In terms of electronics, the quantizing noise generated by the high-speed ADC, circuit design noise, clock stabilization, and digital demodulation noise are considered herein.

Conclusion
This study proposed a method for enhancing the receiver sensitivity of coherent free-space optical (FSO) communication systems, which was enabled by BSPK technology based on LDPC encoding. The following results were obtained: the Doppler effect, resulting from the relative motion between satellites, could be properly addressed by using the proposed two-stage frequencyoffset compensation. With a data rate of 1.25 Gbps corresponding to optical communication, the performance rendering the optical receiving power of −52 dBm and BER of 10 -7 could be achieved through the proposed system. In addition, Considering the resource consumption and implementation for high speed, serial-bit-flip (SBF) algorithm was employed in this experiment to enable the hard decision of LDPC. When the BER magnitude was in the scale of 10-7, the coding gain in the actual experiment was 3.5 dB. It is better than Reed-solomon encoding. Different from conventional DPSK and OOK, the LDPC-encoded BPSK approach yielded a high level of receiving sensitivity in FSO communication, which further demonstrated its superior feasibility. Moreover, the Doppler shift, resulting from the relative motion between satellites, could be solved via the proposed two-stage frequency compensation. Notably, the findings of this experiment can offer reliable technical support for the subsequent construction of FSO communication systems.

Data availability statement
The raw data supporting the conclusion of this article will be made available by the authors, without undue reservation.