AUTHOR=Cruz Carlos , De Vicente Juan 

TITLE=Charge-coupled device readout by digital-correlated double sampling

JOURNAL=Frontiers in Detector Science and Technology

VOLUME=Volume 2 - 2024

YEAR=2024

URL=https://www.frontiersin.org/journals/detector-science-and-technology/articles/10.3389/fdest.2024.1487623

DOI=10.3389/fdest.2024.1487623

ISSN=2813-8031

ABSTRACT=Charge-Coupled Devices (CCDs) play a crucial role in astronomy due to their widespread use in the optical band. CCDs offer high sensibility, low noise, high dynamic range (DR) and high spatial resolution. Recent advances have focused on improving sub-electron noise levels for particle detection and enhancing readout speeds through simulations. The main objective is to replace the analog processing of CCD signals with the implementation of the Digital Correlated Double sampling (DCDS) technique. DCDS offers post-acquisition noise correction through intermittent sampling of an internal reference voltage, providing compact and flexible performance. In this study, DCDS was evaluated using two digital processing systems: a 2.5 MSPS 24-bit ADC board and a 250 MSPS 16-bit ADC FPGA based buffer memory board. Readout noise values at 74 kpix/sec (7.1 e) showed significant improvement over those obtained from analog processing (9.7 e). DCDS implementation demonstrates optimal Signal-to-Noise Ratio (SNR) across a wide range of readout speeds. Parameters such as the sample positions per pixel, the number of samples, and the number of pixels are identified to be essential in achieving a correct gain value.Finally, VHDL-defined hardware implementing DCDS IP core algorithm in a Xilinx Zynq-7000 AP SoC reports a significant improvement in power dissipation (7.1 W) if compared to analog Monsoon CDS circuits (13.6 W). DCDS IP core implementation also reduces background noise up to 34 % contrasted with the DCDS offline readout processing.