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        <title>Frontiers in Detector Science and Technology | Data Acquisitions Methods and Readout Electronics section | New and Recent Articles</title>
        <link>https://www.frontiersin.org/journals/detector-science-and-technology/sections/data-acquisitions-methods-and-readout-electronics</link>
        <description>RSS Feed for Data Acquisitions Methods and Readout Electronics section in the Frontiers in Detector Science and Technology journal | New and Recent Articles</description>
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        <pubDate>2026-05-15T14:29:52.560+00:00</pubDate>
        <ttl>60</ttl>
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        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/fdest.2025.1544824</guid>
        <link>https://www.frontiersin.org/articles/10.3389/fdest.2025.1544824</link>
        <title><![CDATA[High-speed ADC-to-FPGA communication bandwidth optimization with link aggregator]]></title>
        <pubdate>2025-04-25T00:00:00Z</pubdate>
        <category>Brief Research Report</category>
        <author>J. Collado</author><author>V. González</author><author>J. M. Deltoro</author><author>A. Gadea</author>
        <description><![CDATA[In nuclear and high-energy physics experiments, data acquisition systems handle vast amounts of data from thousands of detectors and electronic channels, often reaching hundreds of terabits per second. While modern field programmable gate arrays (FPGAs) offer high-speed transceivers capable of processing such data, a mismatch can arise: individual analog-to-digital converters (ADCs) process lower data rates than FPGA transceivers can efficiently handle. This inefficiency leads to unnecessary usage of more powerful and expensive FPGAs, thus increasing system costs. This paper addresses this issue by proposing a link aggregator method for ADC readout. The solution integrates five universal link aggregator devices within an FPGA mezzanine card (FMC) board, enabling 1-to-1, 2-to-1, 3-to-1, or 4-to-1 multiplexing. The system optimizes FPGA resource utilization with support for up to 40 optical or copper inputs (2.5 Gbps per link) and a 10-line aggregated output (10 Gbps max) via a Vita57.1 FMC connector. A low-cost, low-power FPGA manages the mezzanine board as an intelligent standalone device. This approach significantly reduces hardware requirements and enhances cost-efficiency in high-performance data acquisition systems.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/fdest.2025.1606018</guid>
        <link>https://www.frontiersin.org/articles/10.3389/fdest.2025.1606018</link>
        <title><![CDATA[Editorial: Advancements and challenges in data acquisitions and readout electronics]]></title>
        <pubdate>2025-04-16T00:00:00Z</pubdate>
        <category>Editorial</category>
        <author>Alberto Valero</author><author>Cristina Bedoya</author><author>Luca Fiorini</author>
        <description></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/fdest.2025.1517241</guid>
        <link>https://www.frontiersin.org/articles/10.3389/fdest.2025.1517241</link>
        <title><![CDATA[OBDT-theta, a multi-channel TDC and readout board for the CMS muon drift tubes in HL-LHC]]></title>
        <pubdate>2025-02-12T00:00:00Z</pubdate>
        <category>Original Research</category>
        <author>C. F. Bedoya</author><author>S. Cuadrado</author><author>J. Cuchillo</author><author>D. Eliseev</author><author>N. Esper</author><author>D. Francia</author><author>A. Navarro</author><author>R. Paz</author><author>C. Presser</author><author>I. Redondo</author><author>D. D. Redondo</author><author>J. Sastre</author>
        <description><![CDATA[A new readout board for the digitization of the CMS (Compact Muon Solenoid) Muon Drift Tube (DT) chambers has been designed in order to cope with the increase of occupancy and trigger rates expected during operation under the foreseen luminosity in the HL-LHC (High Luminosity Large Hadron Collider). The board OBDT-theta (On-detector Board for Drift Tubes) can perform the time digitization and readout of the DT chamber signals measuring the z-coordinate (along the beam axis) of CMS. A total of 228 channels can be digitized with a time bin of 0.78 ns and full streaming of all the DT chamber signals can be made through optical links into the CMS counting room. There, the full detector information can be available to perform the trigger and event building logic. The different functionality of the OBDT-theta board has been verified and the overall architecture has been validated through specific tests. The OBDT-theta architecture and main functionality will be presented in this contribution, showing the suitability of the design for the expected functionality during the HL-LHC.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/fdest.2025.1484647</guid>
        <link>https://www.frontiersin.org/articles/10.3389/fdest.2025.1484647</link>
        <title><![CDATA[Wi-Fi/LoRa communication systems for fire and seismic-risk mitigation and health monitoring]]></title>
        <pubdate>2025-02-07T00:00:00Z</pubdate>
        <category>Review</category>
        <author>José Sánchez del Río Sáez</author><author>Víctor Aragonés</author><author>Tomás Sánchez Villaluenga</author><author>L. Davila-Gomez</author><author>Sofía Paramio Martínez</author><author>Antonio Vázquez-López</author><author>Yolanda Ballesteros</author><author>Vanesa Martínez</author><author>José Luis Jiménez</author><author>Abdulmalik Yusuf</author><author>Xiaolu Li</author><author>Xiang Ao</author><author>Jie Xiu</author><author>De-Yi Wang</author>
        <description><![CDATA[This article summarizes the work performed by the authors in developing, during the last 2 years, several portable and wireless sensor systems that allowed the analysis of signals collected from multiple sensors based on the Internet of Things (IoT) in emergency contexts. These include fires and earthquakes, situations in which citizens suffer from poor health; participation of individuals in highly physical sports; or cases of materials used in buildings and other structures being subjected to high stress due to natural catastrophes other than the aforementioned fires and earthquakes. Novel material sensors like MXene paper or wallpaper-based ones used as fire detectors and operating remotely via Wi-Fi and LoRa are presented. Furthermore, a Wi-Fi communication system, physically connected to a commercial micro-controller, monitored the temperature and luminosity data. Other devices, such as IoT wireless systems operating under the LoRa protocol in the 868-MHz and 2.4-GHz band region and using RFM95 radio modules as possible risk advisers, are described. For the latter, the sensors integrated were triboelectric energy nanogenerators (TENGs). In addition, TENG smart masks with LoRa emitters were used and played an important role in risk mitigation. As novel systems, an STM32 LoRa board allowed monitoring of the health (heart rate and oxygen saturation) of athletes involved in combat sports, with a nano-IoT Arduino 33 chip being used for monitoring the electrical resistance change in some composite materials. Some of these developments, especially the previously mentioned one, can play an important role in structural health monitoring (SHM) by examining the mechanical properties during service operations in aviation or aerospace fields. A comparison of these systems allowed them to be classified according to the most fitting application.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/fdest.2024.1502834</guid>
        <link>https://www.frontiersin.org/articles/10.3389/fdest.2024.1502834</link>
        <title><![CDATA[Harnessing hardware acceleration in high-energy physics through high-level synthesis techniques]]></title>
        <pubdate>2025-01-14T00:00:00Z</pubdate>
        <category>Methods</category>
        <author>Pelayo Leguina</author><author>Santiago Folgueras</author>
        <description><![CDATA[At the Large Hadron Collider, the vast amount of data from experiments demands not only sophisticated algorithms but also substantial computational power for efficient processing. This paper introduces hardware acceleration as an essential advancement for high-energy physics data analysis, focusing specifically on the application of High-Level Synthesis (HLS) to bridge the gap between complex software algorithms and their hardware implementation. We will explore how HLS facilitates the direct implementation of software algorithms into hardware platforms such as FPGAs, enhancing processing speeds and enabling real-time data analysis. This will be highlighted through the case study of a track-finding algorithm for muon reconstruction with the CMS experiment, demonstrating HLS’s role in translating computational tasks into high-speed, low-latency hardware solutions for particle detection and reconstruction. Key techniques in HLS, including parallel processing, pipelining, and memory optimization, will be discussed, illustrating how they contribute to the efficient acceleration of algorithms in high-energy physics. We will also cover design methodologies and iterative processes in HLS to optimize performance and resource utilization, alongside a brief mention of additional techniques like algorithm approximation and hardware/software co-design. In short, this paper will underscore the potential of hardware acceleration in high-energy physics research, emphasizing HLS as a powerful tool for physicists to enhance computational efficiency and foster groundbreaking discoveries.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/fdest.2024.1487623</guid>
        <link>https://www.frontiersin.org/articles/10.3389/fdest.2024.1487623</link>
        <title><![CDATA[Charge-coupled device readout by digital-correlated double sampling]]></title>
        <pubdate>2024-11-13T00:00:00Z</pubdate>
        <category>Original Research</category>
        <author>Carlos Cruz</author><author>Juan De Vicente</author>
        <description><![CDATA[Charge-coupled devices (CCDs) play crucial roles in astronomy owing to their widespread use in the optical band, offering high sensibility, low noise, high dynamic range, and high spatial resolution. Recent advancements in CCDs have focused on improving the sub-electron noise levels for particle detection and enhancing readout speeds through simulation studies. The main objective of this study is to replace the analog processing of CCD signals using the digital-correlated double sampling (DCDS) technique. DCDS allows post-acquisition noise correction through intermittent sampling of an internal reference voltage to provide compact and flexible performance. In this study, DCDS was evaluated using two digital processing systems, namely, a 2.5 mega-samples per second (MSPS) 24-bit analog-to-digital converter (ADC) board and a 250 MSPS 16-bit ADC field-programmable-gate-array( FPGA)-based buffer memory board. The readout noise value at 74 kpix/s (7.1 e) was a significant improvement over that obtained with analog processing (9.7 e). The DCDS implementation demonstrates optimal signal-to-noise ratio for a wide range of readout speeds. Parameters such as the sample positions per pixel, number of samples, and number of pixels were identified to be essential in achieving an accurate gain value. Finally, hardware implementation of the DCDS IP core algorithm on a Xilinx Zynq-7000 AP system-on-a-chip (SoC) showed a significant improvement in power dissipation (7.1 W) compared to the analog Monsoon correlated double sample (CDS) circuit (13.6 W). The DCDS IP core implementation also showed a background noise reduction of up to 34% compared to DCDS offline readout processing using a Python algorithm.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/fdest.2023.1264123</guid>
        <link>https://www.frontiersin.org/articles/10.3389/fdest.2023.1264123</link>
        <title><![CDATA[The PreProcessor module for the ATLAS Tile calorimeter at the HL-LHC]]></title>
        <pubdate>2023-09-19T00:00:00Z</pubdate>
        <category>Original Research</category>
        <author>A. Valero</author><author>F. Carrió</author><author>L. Fiorini</author><author>A. Cervelló</author><author>D. Hernandez</author><author>A. Ruiz Martinez</author>
        <description><![CDATA[The Large Hadron Collider (LHC) has played a crucial role in advancing our understanding of fundamental physics. With the discovery of the Higgs boson in 2012, the ATLAS and CMS experiments have made significant progess in studying its properties and searching for new physics beyond the Standard Model. To maintain and expand the LHC’s discovery potential, the High-Luminosity LHC (HL-LHC) project is planned as a major upgrade. As part of this upgrade, the ATLAS experiment has developed a comprehensive roadmap for upgrades, including the installation of new detector components and advancements in data acquisition and processing systems. A crucial component of these enhancements involves the complete replacement of the ATLAS central Tile hadronic calorimeter readout electronics. This upgrade aims to optimize the system’s ability to handle higher data rates and improve its resilience to radiation. Through these comprehensive improvements, the ATLAS experiment aims to meet the requirements and seize the opportunities presented by the HL-LHC era. This paper presents the design and architecture of the TilePPr (Tile PreProcessor) module, which serves as a crucial interface between the on-detector electronics and the central systems of the ATLAS experiment, including Data Acquisition, Detector Control, and Trigger systems. The TilePPr module is based on the Advanced Telecommunications Computing Architecture (ATCA) and incorporates high-speed optical links, communication interfaces, and data processing capabilities. Through a series of certification tests, the module has demonstrated its compliance with industry standards and functional requirements, confirming its suitability for seamless integration into the ATLAS experiment during the HL-LHC phase.]]></description>
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