AUTHOR=Seo Dong-Hyun , Chatterjee Baibhab , Scott Sean M. , Valentino Daniel J. , Peroulis Dimitrios , Sen Shreyas 

TITLE=Design and Analysis of a Resistive Sensor Interface With Phase Noise-Energy-Resolution Scalability for a Time-Based Resistance-to-Digital Converter

JOURNAL=Frontiers in Electronics

VOLUME=Volume 3 - 2022

YEAR=2022

URL=https://www.frontiersin.org/journals/electronics/articles/10.3389/felec.2022.792326

DOI=10.3389/felec.2022.792326

ISSN=2673-5857

ABSTRACT=This paper presents the design and analysis of a resistive sensor interface with three different designs of phase noise-energy-resolution scalability in time-based resistance to digital converters (RDC), including testchip implementations and measurements, targeted towards either minimizing the energy/conversion step or maximizing bit-resolution. The implemented RDCs consist of a 3-stage differential ring oscillator which is current starved with the resistive sensor, a differential to single ended amplifier, digital modules and serial interface. The first RDC design (baseline) included the basic structure of time-based RDC and targeted low energy/conversion step. The second RDC design (goal: higher-resolution) aimed to improve the rms jitter/phase noise of the oscillator with help of speed-up latches, to achieve higher bit-resolution as compared to the first RDC design. The third RDC design (goal: process portability) reduced the power consumption by scaling the technology with the improved phase-noise design, achieving 1-bit better resolution as that of the second RDC design. Using a time-based implementation, the RDCs exhibit energy-resolution scalablity, and consume a measured power of 861nW with 18-bit resolution in design 1 in TSMC 0.35μm technology (with 10ms read-time, with one readout every second). Measurements of design 2 and 3 demonstrate power consumption of 19.2μW with 20-bit resolution using TSMC 0.35μm, and 17.6μW with 20-bit resolutions using TSMC 0.18μm, respectively (both with 10ms read-time, repeated every second). With 30ms read-time, design 3 achieves 21-bit resolution, which is the highest resolution reported for a time-based ADC. The 0.35μm time-based RDC is the lowest-power time-based ADC reported, while the 0.18μm time-based RDC with speed-up latch offers the highest resolution. The active chip-area for all 3-designs are less than 1.1 mm².