CMOS-Based Physically Unclonable Functions: Guidelines on Properties and Design

Abstract

Physically unclonable functions (PUFs) based on CMOS technology have become essential security primitives for ASIC identification and authentication. Linking intrinsic transistor-level variations to the randomness of responses generated at the PUF system level is a fundamental challenge for ASIC designers aiming to integrate CMOS-based PUFs into electronic chips. This paper discusses the key intrinsic fabrication variations in bulk MOSFETs. It presents guidelines for leveraging these variations to obtain measurable yet physically unclonable and mathematically unmodelable unique and reliable imprints for ASICs. The study reviews various PUF architectures, their practical applications, and the challenges associated with their implementation. The article also presents a comprehensive yet easy-to-follow mathematical framework to characterize PUF metrics and testing methodologies. This review aims to provide an accessible introduction for novel CMOS-based PUF designers by addressing the primary sources of intrinsic variations in planar transistors and offering recommendations at the schematic, layout, masking, and fabrication levels. The review article also touches on the early types of electronic PUFs, parameters, applications, and limitations. This study provides an accessible tool for these vast topics while adhering to the publication's scope and size constraints.