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        <title>Frontiers in Electronics | Nano- and Microelectronics section | New and Recent Articles</title>
        <link>https://www.frontiersin.org/journals/electronics/sections/nano--and-microelectronics</link>
        <description>RSS Feed for Nano- and Microelectronics section in the Frontiers in Electronics journal | New and Recent Articles</description>
        <language>en-us</language>
        <generator>Frontiers Feed Generator,version:1</generator>
        <pubDate>2026-04-04T12:50:15.281+00:00</pubDate>
        <ttl>60</ttl>
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        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2026.1799771</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2026.1799771</link>
        <title><![CDATA[Metal penetration induced interfacial challenges and engineering strategies in OSV devices]]></title>
        <pubdate>2026-03-18T00:00:00Z</pubdate>
        <category>Review</category>
        <author>Dongfang Shi</author>
        <description><![CDATA[Spintronics has emerged as an important research topic in the field of information communication, and organic spin-valve (OSV) devices are fabricated for demonstration and research in this area. Metal penetration of the top ferromagnetic electrodes into organic spacer layers has long been a pervasive challenge in OSV devices. Originating from evaporative deposition and facilitated by the conventional spacer layers, such penetration can severely degrade device performance and even lead to a complete loss of magnetoresistance (MR) signals. In this review, we first summarize the characterization techniques, experimental signatures, physical origins, and effects of metal penetration. Then, we further review diverse strategies developed to suppress metal penetration along the development of spintronics, including interlayer insertion, spacer material selection, electrode preparation and transfer, spacer layer preparation, and junction-area engineering, underscoring their respective advantages and limitations in terms of robustness, reproducibility, purity, and scalability. Finally, we conclude emerging opportunities enabled by metal-organic frameworks (MOFs) as a next-generation spacer material. Owing to their intrinsic properties, MOFs can hierarchically suppress metal penetration via geometric regulation, physical robustness, and local chemical coordination, while preserving clean spin-injection interfaces. We also outlined future research directions towards scalable fabrication and practical implementation of MOF-based spacers, as such optimizations can comprehensively improve the device performance, based on the effective restraint of metal penetration.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2025.1648721</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2025.1648721</link>
        <title><![CDATA[Analytical prediction of thermomechanical shear strain in solder joints with FEA validation in electronic packaging]]></title>
        <pubdate>2025-09-15T00:00:00Z</pubdate>
        <category>Original Research</category>
        <author>Utkarsha Bhetuwal</author><author>Jiang Zhou</author><author>Xuejun Fan</author>
        <description><![CDATA[This paper presents a closed-form analytical model for predicting shear strain in chip-on-board assemblies with an array of solder balls. While the classical analytical formula estimates shear strain based on a configuration with a single solder joint at each end of the chip, it fails to account for the distributed nature of real assemblies. By applying compatibility conditions along the chip/solder ball and PCB/solder ball interfaces, and employing beam theory, the proposed model incorporates key geometric and material parameters, including chip and PCB dimensions, solder ball diameter, height, pitch, and elastic moduli, enabling accurate prediction of mechanical response under thermal loading. Results show that the classical model overestimates shear strain by more than 50 times compared to finite element analysis (FEA), whereas the proposed method yields results consistent with FEA. Hence, the proposed analytical solution presented in the paper demonstrates a significant improvement over the classical formula in prediction of shear strain. The new model reveals that in a fully populated array layout, the maximum shear strain at the outermost solder joint remains nearly constant with increasing chip size. The analysis also indicates that inner solder joints contribute minimally to mechanical support, suggesting that depopulated array designs may not compromise reliability. Additional parametric studies demonstrate that reducing the thickness or stiffness of the chip or PCB decreases overall strain levels. These findings are validated by finite element simulations. The paper concludes with a discussion of future work to address normal strain effects and inelastic behaviors in solder joints.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2025.1651937</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2025.1651937</link>
        <title><![CDATA[Future prospect of anisotropic 2D tin sulfide (SnS) for emerging electronic and quantum device applications]]></title>
        <pubdate>2025-07-28T00:00:00Z</pubdate>
        <category>Perspective</category>
        <author>Abdus Salam Sarkar</author>
        <description><![CDATA[The family of anisotropic two-dimensional (2D) emerging materials is rapidly evolving due to their low crystal symmetry and in-plane structural anisotropy. Among these, 2D tin sulfide (SnS) has gained significant attention because of its distinctive crystalline symmetry and the resulting extraordinary anisotropic physical properties. This perspective explores recent developments in anisotropic 2D SnS. In particular, it highlights advances in isolating high-quality SnS monolayers (1L-SnS) and in applying advanced techniques for anisotropic characterization. The discussion continues with an overview of the anisotropic optical and electronic properties of SnS, followed by recent progress in emerging electronic device applications, including energy conversion and storage, neuromorphic (synaptic) systems, spintronics and quantum technologies. In addition to presenting significant research findings on SnS, this perspective outlines current limitations and discusses emerging opportunities and future prospects for its application in quantum devices.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2025.1568377</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2025.1568377</link>
        <title><![CDATA[An RRAM-based implementation of a template matching circuit for low-power analogue classification]]></title>
        <pubdate>2025-04-30T00:00:00Z</pubdate>
        <category>Original Research</category>
        <author>Patrick Foster</author><author>Georgios Papandroulidakis</author><author>Alex Serb</author><author>Spyros Stathopoulos</author><author>Themis Prodromakis</author>
        <description><![CDATA[Recent advances in machine learning and neuro-inspired systems enabled the increased interest in efficient pattern recognition at the edge. A wide variety of applications, such as near-sensor classification, require fast and low-power approaches for pattern matching through the use of associative memories and their more well-known implementation, Content Addressable Memories (CAMs). Towards addressing the need for low-power classification, this work showcases an RRAM-based analogue CAM (ACAM) intended for template matching applications, providing a low-power reconfigurable classification engine for the extreme edge. The circuit uses a low component count at 6T2R2M, comparable with the most compact existing cells of this type. In this work, we demonstrate a hardware prototype, built with Commercial-Off-The-Shelf (COTS) components for the MOSFET-based circuits, that implements rows of 6T2R2M employing TiOx-based RRAM devices developed in-house, showcasing competitive matching window configurability and definition. Furthermore, through simulations, we validate the performance of the proposed circuit by using a commercially available 180 nm technology and in-house RRAM data-driven model to assess the energy dissipation, exhibiting 60 pJ per classification event.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2025.1493911</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2025.1493911</link>
        <title><![CDATA[Cu/Co meta-interconnects for 112 Gbps high speed applications]]></title>
        <pubdate>2025-02-14T00:00:00Z</pubdate>
        <category>Brief Research Report</category>
        <author>Hae-in Kim</author><author>Alexander Wilcher</author><author>Renuka Bowrothu</author><author>Yong-Kyu Yoon</author>
        <description><![CDATA[This paper presents an innovative interconnect approach called “meta-interconnect,” which utilizes a combination of copper (Cu) and cobalt (Co) metaconductor (Cu/Co-MC) to enhance signal integrity in the millimeter-wave (mm-wave) spectrum. The primary objective is to demonstrate reduced conductor losses from the skin effect compared to Cu at the 112 Gbps Nyquist frequency of 28 GHz. For the first time, a comprehensive parametric analysis is conducted using both simulation and experimentation methods to suppress the skin effect with Cu/Co-MC. Based on the optimization of Cu/Co-MC-based coplanar waveguide (CPW) transmission lines, a minimum insertion loss of only 0.08 dB/mm at 28 GHz, which is 0.06 dB/mm less than that of the Cu counterpart, has been demonstrated, which represents a 42.86% reduction in conductor power losses. Additionally, Cu/Co-MC-based CPWs meet the sub-0.1 dB/mm channel loss target. The study verifies the impact that the thickness and number of Cu/Co-MC layers have on device performances. This provides valuable insights into the optimizing MC configurations, which in this study are 250 nm thick Cu and 40 nm thick Co. Cu/Co-MC pairs with optimized layers and total thicknesses demonstrate significant improvements in insertion loss and thermal noise. These findings highlight the potential benefits of the Cu/Co-MC-based meta-interconnect technology for data center high-speed serial bus applications, offering a promising solution for achieving high signal integrity in the mm-wave spectrum, contributing to the overall understanding and its MCs translation to commercial applications.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2025.1497940</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2025.1497940</link>
        <title><![CDATA[Comprehensive analysis of In0.53Ga0.47As SOI-FinFET for enhanced RF/wireless performance]]></title>
        <pubdate>2025-02-03T00:00:00Z</pubdate>
        <category>Original Research</category>
        <author>Priyanka Agrwal</author><author>Ajay Kumar</author>
        <description><![CDATA[This paper comprehensively analyses the RF (Radio Frequency) and wireless performance characteristics of high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs-SOI-FinFET). Firstly, the fundamental operating principles and unique features of InGaAs-SOI-FinFET are discussed, highlighting their three-dimensional fin structure and improved electrostatic control, which contributes to enhanced electrostatic integrity and reduced leakage currents compared to traditional CMOS technologies. The linearity performance of InGaAs-SOI-FinFET focuses on parameters such as third-order intercept point (IP3) and linearity metrics in analog circuits. The influence of device geometry, biasing schemes, and operating conditions on linearity characteristics and strategies for enhancing linearity while maintaining high-frequency performance is examined. Subsequently, an in-depth analysis of the RF performance metrics, such as fT, fMAX, TFP, GFP and GTFP. Thus, emerging trends and challenges in leveraging InGaAs-SOI-FinFET for RF and linearity-critical applications include circuit design, process integration, and reliability considerations.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2024.1515860</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2024.1515860</link>
        <title><![CDATA[Warpage in wafer-level packaging: a review of causes, modelling, and mitigation strategies]]></title>
        <pubdate>2025-02-03T00:00:00Z</pubdate>
        <category>Review</category>
        <author>Pallavi Praful</author><author>Chris Bailey</author>
        <description><![CDATA[Wafer-level packaging (WLP) is a pivotal semiconductor packaging technology that enables heterogeneously integrated advanced semiconductor packages with high-density electrical interconnections through its efficient and highly reliable manufacturing processes. Within this domain, fan-out wafer-level packaging has gained prominence due to its potential for high integration capacity, scalability, and performance on a smaller footprint. This review examines FOWLP technology and its associated challenges, primarily warpage. As semiconductor companies strive to develop cutting-edge packages, wafer warpage remains an intrinsic and persistent issue affecting yield and reliability at both the wafer and package levels. Warpage characterization techniques and modeling approaches, including theoretical, numerical, and emerging artificial intelligence and machine learning (AI/ML) methods, have been analyzed. The structural parameters and properties of the constituent materials of the reconstituted wafer and the FOWLP process have been considered to evaluate the effectiveness of these methods in predicting and analyzing warpage. Potential directions and limitations in warpage prediction and mitigation have been outlined for future research for more reliable and high-performance FOWLP solutions.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2025.1506112</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2025.1506112</link>
        <title><![CDATA[Electronics packaging materials and component-level degradation monitoring]]></title>
        <pubdate>2025-01-31T00:00:00Z</pubdate>
        <category>Review</category>
        <author>Adwait Inamdar</author><author>Willem D. Van Driel</author><author>GuoQi Zhang</author>
        <description><![CDATA[Electronic components are complex systems consisting of a combination of different materials, which undergo degenerative changes over time following the second law of thermodynamics. The loss of their quality or functionality is reflected in degraded performance or behaviour of electronic components, which can lead to failures during their operation lifetime. Thus, it is crucial to understand the physics of material degradation and the factors causing it to ensure component reliability. This paper focuses on the physics-of-degradation of packaging materials, which are typically exposed the most to the environmental and operating loads. The content of this article is organised into three parts. First, an overview of the packaging technology and encapsulating materials is presented. Then, the most common degradation-causing factors and package-associated failure modes are reviewed. Lastly, the hardware requirements are discussed, including specialised sensors, measurement techniques, and Digital Twins, to capture the degradation effects and facilitate component-level health monitoring for microelectronics.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2023.1277927</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2023.1277927</link>
        <title><![CDATA[Two-dimensional semiconductors based field-effect transistors: review of major milestones and challenges]]></title>
        <pubdate>2023-11-08T00:00:00Z</pubdate>
        <category>Mini Review</category>
        <author>Keshari Nandan</author><author>Amit Agarwal</author><author>Somnath Bhowmick</author><author>Yogesh S. Chauhan</author>
        <description><![CDATA[Two-dimensional (2-D) semiconductors are emerging as strong contenders for the future of Angstrom technology nodes. Their potential lies in enhanced device scaling and energy-efficient switching compared to traditional bulk semiconductors like Si, Ge, and III-V compounds. These materials offer significant advantages, particularly in ultra-thin devices with atomic scale thicknesses. Their unique structures enable the creation of one-dimensional nanoribbons and vertical and lateral heterostructures. This versatility in design, coupled with their distinctive properties, paves the way for efficient energy switching in electronic devices. Moreover, 2-D semiconductors offer opportunities for integrating metallic nanoribbons, carbon nanotubes (CNT), and graphene with their 2-D channel materials. This integration helps overcome lithography limitations for gate patterning, allowing the realization of ultra-short gate dimensions. Considering these factors, the potential of 2-D semiconductors in electronics is vast. This concise review focuses on the latest advancements and engineering strategies in 2-D logic devices.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2022.1091343</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2022.1091343</link>
        <title><![CDATA[Breakdown-limited endurance in HZO FeFETs: Mechanism and improvement under bipolar stress]]></title>
        <pubdate>2022-12-21T00:00:00Z</pubdate>
        <category>Original Research</category>
        <author>Kasidit Toprasertpong</author><author>Mitsuru Takenaka</author><author>Shinichi Takagi</author>
        <description><![CDATA[Breakdown is one of main failure mechanisms that limit write endurance of ferroelectric devices using hafnium oxide-based ferroelectric materials. In this study, we investigate the gate current and breakdown characteristics of Hf0.5Zr0.5O2/Si ferroelectric field-effect transistors (FeFETs) by using carrier separation measurements to analyze electron and hole leakage currents during time-dependent dielectric breakdown (TDDB) tests. Rapidly increasing substrate hole currents and stress-induced leakage current (SILC)-like electron currents can be observed before the breakdown of the ferroelectric gate insulator of FeFETs. This apparent degradation under voltage stress is recovered and the time-to-breakdown is significantly improved by interrupting the TDDB test with gate voltage pulses with the opposite polarity, suggesting that defect redistribution, rather than defect generation, is responsible for the trigger of hard breakdown.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2022.954661</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2022.954661</link>
        <title><![CDATA[Quantization and sparsity-aware processing for energy-efficient NVM-based convolutional neural networks]]></title>
        <pubdate>2022-08-12T00:00:00Z</pubdate>
        <category>Original Research</category>
        <author>Han Bao</author><author>Yifan Qin</author><author>Jia Chen</author><author>Ling Yang</author><author>Jiancong Li</author><author>Houji Zhou</author><author>Yi Li</author><author>Xiangshui Miao</author>
        <description><![CDATA[Nonvolatile memory (NVM)-based convolutional neural networks (NvCNNs) have received widespread attention as a promising solution for hardware edge intelligence. However, there still exist many challenges in the resource-constrained conditions, such as the limitations of the hardware precision and cost and, especially, the large overhead of the analog-to-digital converters (ADCs). In this study, we systematically analyze the performance of NvCNNs and the hardware restrictions with quantization in both weight and activation and propose the corresponding requirements of NVM devices and peripheral circuits for multiply–accumulate (MAC) units. In addition, we put forward an in situ sparsity-aware processing method that exploits the sparsity of the network and the device array characteristics to further improve the energy efficiency of quantized NvCNNs. Our results suggest that the 4-bit-weight and 3-bit-activation (W4A3) design demonstrates the optimal compromise between the network performance and hardware overhead, achieving 98.82% accuracy for the Modified National Institute of Standards and Technology database (MNIST) classification task. Moreover, higher-precision designs will claim more restrictive requirements for hardware nonidealities including the variations of NVM devices and the nonlinearities of the converters. Moreover, the sparsity-aware processing method can obtain 79%/53% ADC energy reduction and 2.98×/1.15× energy efficiency improvement based on the W8A8/W4A3 quantization design with an array size of 128 × 128.]]></description>
      </item><item>
        <guid isPermaLink="true">https://www.frontiersin.org/articles/10.3389/felec.2022.825077</guid>
        <link>https://www.frontiersin.org/articles/10.3389/felec.2022.825077</link>
        <title><![CDATA[Exploiting Non-idealities of Resistive Switching Memories for Efficient Machine Learning]]></title>
        <pubdate>2022-03-25T00:00:00Z</pubdate>
        <category>Mini Review</category>
        <author>Victor Yon</author><author>Amirali Amirsoleimani</author><author>Fabien Alibart</author><author>Roger G. Melko</author><author>Dominique Drouin</author><author>Yann Beilliard</author>
        <description><![CDATA[Novel computing architectures based on resistive switching memories (also known as memristors or RRAMs) have been shown to be promising approaches for tackling the energy inefficiency of deep learning and spiking neural networks. However, resistive switch technology is immature and suffers from numerous imperfections, which are often considered limitations on implementations of artificial neural networks. Nevertheless, a reasonable amount of variability can be harnessed to implement efficient probabilistic or approximate computing. This approach turns out to improve robustness, decrease overfitting and reduce energy consumption for specific applications, such as Bayesian and spiking neural networks. Thus, certain non-idealities could become opportunities if we adapt machine learning methods to the intrinsic characteristics of resistive switching memories. In this short review, we introduce some key considerations for circuit design and the most common non-idealities. We illustrate the possible benefits of stochasticity and compression with examples of well-established software methods. We then present an overview of recent neural network implementations that exploit the imperfections of resistive switching memory, and discuss the potential and limitations of these approaches.]]></description>
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