In this paper, a four-terminal DC grid system is taken as an example, as shown in Figure 1A. The system consists of four VSCs, referred to as VSC₁, VSC₂, VSC₃, and VSC₄. There are four pairs of overhead lines, and their RLC equivalent circuit model (Li et al., 2017b) is shown in Figure 1B for short-circuit fault current calculation. According to (Belda et al., 2018; Yang et al., 2018), MMC converters can be represented by an RLC equivalent circuit under short-circuit faults. In this model, a series RLC branch is used to represent the VSC _i , which includes an internal resistance R _i , limiting current inductance L _i and discharging capacitance C _i , where i = 1,2,3,4. According to transmission line theory (Li et al., 2016), a pair of overhead line is modeled as an RL series circuit, with R _ij and L _ij representing the overhead line between VSC _i and VSC _j . The nodes n i + / n i − representnthe positive/negative pole of VSC _i .

To establish the RLC equivalent circuit, it is assumed that a short-circuit fault occurs in the middle position of the power transmission line between VSC₁ and VSC₂. So, the number of pairs of overhead lines increases from four to five. Node n ₀ is the fault point in Figure 1B, and R ₁₀/₂₀ and L ₁₀/₂₀ are the equivalent resistance and inductance of the overhead line between nodes n ₁/₂ and n ₀. The parameter calculation method for this model has been developed in (Li et al., 2017a).

In the RLC equivalent circuit, the circular arrows indicate the orientations of the loops chosen for writing the KVL equation. We conceive of fictitious circulating loop currents, with references given by the loop orientations. Examination of the RLC equivalent circuit shows that these loop currents are identical with the branch currents i ₁, i ₂, i ₃, i ₄ and i ₅, which are the currents through the equivalent inductances L ₁₀, L ₂₀, L ₂₄, L ₃₄, and L ₁₃. So, these loop currents are the state variable of the equivalent inductances of the overhead lines.

On the other hand, the voltages (u _c1, u _c2, u _c3 and u _c4) across the discharging capacitance C ₁, C ₂, C ₃, and C ₄ are also another set of state variables. To obtain a compact state equation, the loop currents rector i , the capacitance voltages rector u and its current rector i _c are defined as follows, i = i 1 , i 2 , i 3 , i 4 , i 5 b = 5 T i c = i c 1 , i c 2 , i c 3 , i c 4 n = 4 T u = u c 1 , u c 2 , u c 3 , u c 4 n = 4 T (1)

By using KVL and VAR, the loop current equation can be obtained in matrix form, A × u = R × i + L × i ˙ (2)

Where A is an incidence matrix, R and L are parameter matrices, referred to respectively as the resistance matrix and the inductance matrix, which will be introduced later.

In Figure 1B, four capacitances, such as C ₁, C ₂, C ₃ and C ₄, are associated with four independent capacitance-voltage state variables. On the other hand, although there are fourteen inductances, there are only five independent inductance current state variables since each independent loop corresponds to a unique independent inductance (Balabanian and Bickart, 1969). Therefore, the RLC equivalent circuit consists of nine state variables, but the Eq. 2 include only five loop current equations. Thus, it is necessary to write the remaining four equations for the state variables.

Application of KCL, the node current equations for nodes n₁, n₂, n₃ and n₄ can be written as i c = − A T i (4)

It is observed from the Eq. 4 that the capacitance current is not an independent state variable, which the independent inductance current state variables can express.

According to the constraint relationship of the capacitance voltage and current through each VSC equivalent circuit, their constraint equations are written as u ˙ c = C i c , C = c i j , c i j = 1 / C i , i = j 0 , i ≠ j (5)

Where C is a diagonal matrix.

Substituting the equation Eq. 4 into Eq. 5, we can get the node equation, u ˙ c = P × i , P = − C A T (6)

The final differential equation set are given as A × u = R × i + L × i ˙ u ˙ c = P × i (7)

By using the Eq. 7, the DC short fault currents of MTDC grid can be promptly and accurately calculated.

Figure 4A shows the equivalent circuit of Y-Delta transformation in the s-domain for the virtual node n ₅ in Figure 3, which is a time-domain circuit. There are two circuits named interior and exterior circuit, respectively. The interior circuit is a Why-type circuit, and the exterior circuit is its Delta-type equivalent circuit. In the s-domain circuit, an inductance L is expressed as an inductance L series with a voltage source L× i (0), where i (0) is the initial current value through the inductance L. The resistance R shares an identical form in the time domain.

In order to determine the parameters of the Delta equivalent circuit, labelled as L _Δ, R _∆ and i _Δ, a circuit complete response can be broken into the natural response and the forced response (Alexander and Sadiku, 2013). Therefore, the circuit shown in Figure 4A can also be separated into the natural and forced response circuits, as shown in Figures 4B,C.

For the natural circuit shown in Figure 4B, the resistance R and inductance L are considered short circuits, because the input currents i ₁, i ₂ and i ₃ are zero. By using KVL, the inductance current initial value of the Delta equivalent circuit can be obtained as, i Δ 41 0 − = − L 15 i 15 0 − + L 54 i 45 0 − L Δ 41 i Δ 34 0 − = L 35 i 35 0 − + L 54 i 54 0 − L Δ 34 i Δ 13 0 − = L 15 i 15 0 − − L 35 i 35 0 − L Δ 13 (8)

For the force circuit shown in Figure 4C, all voltage sources can be considered short circuits since the initial value of inductance current equals zero. By using the conversion rule for Wye to Delta (Alexander and Sadiku, 2013), the following formula can be obtained, R Δ 13 + s L Δ 13 = R 15 + s L 15 R 35 + s L 35 R 45 + s L 45 + R 35 + s L 35 + R 15 + s L 15 R Δ 34 + s L Δ 34 = R 35 + s L 35 R 45 + s L 45 R 15 + s L 15 + R 35 + s L 35 + R 45 + s L 45 R Δ 41 + s L Δ 41 = R 15 + s L 15 R 45 + s L 45 R 35 + s L 35 + R 15 + s L 15 + R 45 + s L 45 (9)

In DC grid, the equivalent resistance of an overhead line is much bigger than the equivalent inductance, Eq. 9 can be simplified, and the R and L expressions of the Delta equivalent circuit can be written as. R Δ 13 ≈ R 15 R 35 R 45 + R 35 + R 15 , L Δ 13 ≈ L 35 + L 15 R Δ 34 ≈ R 35 R 45 R 15 + R 35 + R 45 , L Δ 34 ≈ L 35 + L 45 R Δ 41 ≈ R 35 R 45 R 35 + R 15 + R 45 , L Δ 41 ≈ L 15 + L 45 (10)

By using the proposed Y-Delta transformation in the s-domain, the virtual node n ₅ in the radial four-terminal dc grid shown in Figure 3 can be eliminated, obtaining its equivalent circuit without virtual node, as shown in Figure 5. In this equivalent circuit, there is not any virtual node. So, one can use the proposed systematic formulation of the differential equation set developed in Section 2 to write its differential equation set.

Figure 6B shows a typical I-V characteristic curve of MOA, which is generally separated into four regions: the normal operational region, pre-breakdown region, breakdown region, and high current region (Martinez and Durbak, 2005). There are two voltage parameters, U _r is the rated voltage and U _ref is the reference voltage.

In CLCB, MOA is utilized to clamp the maximum to U _ref and dissipate the energy of fault current. It is difficult to analyze a CLCB circuit because MOA is a nonlinear circuit element. A piece-wise linear I-V curve of MOA, as shown in Figure 6C, is used for the pre-breakdown region and breakdown region to simplify analysis of CLCB circuit, since it is allowed to operate in the normal operational region, pre-breakdown region and breakdown region.

As shown in Figure 6C, four piece straight lines are used to describe the I-V curve, and its equivalent circuit is depicted in Figure 6D. When the MOA operates in the normal operational region, the current flowing through it is approximately several mA, it can be considered as an open circuit. Consequently, the switch S₀ remains open in the equivalent circuit. If U _r ≦ u _moa < U _a, both switches of S ₀ and S ₁ close, but the switches of S ₂, S ₃, and S ₄ remain open. In this scenario, the equivalent circuit is a voltage source U _r series with the resistor R _a. Hence, the piecewise linear model of MOA can be respectively expressed as. R m o v = R m o v 0 = ∞ , u m o v ≤ U r , S 0 = o f f R m o v 1 = t g α 1 , U r < u m o v ≤ U a , S 0 / S 1 = o n R m o v 2 = t g α 2 , U a < u m o v ≤ U b , S 0 / S 2 = o n R m o v 3 = t g α 3 , U b < u m o v ≤ U r e f , S 0 / S 3 = o n R m o v 4 = 0 , u m o v > U r e f , S 0 / S 4 = o n (11) i m o v = 0 , u m o v ≤ U r u m o v − U r / R m o v 1 , U r < u m o v ≤ U a u m o v − U a / R m o v 2 + I a , U a < u m o v ≤ U b u m o v − U b / R m o v 3 + I b , U b < u m o v ≤ U r e f u m o v = U r e f , u m o v > U r e f (12)

Figure 7A illustrates an inductive-CLCB circuit [21]. The circuit consists of L ₁ , which functions as the limiting current inductor of the VSC and serves as the primary side of the transformer, and L ₂ , which acts as the secondary side. Under normal conditions, IGBT T ₁, T ₃ and UFD₁ are turned on to the normal current to flow through L ₁-T ₁-UFD₁-T ₃, as indicated by the blue dotted line in Figure 7A. In this case, there is no current flowing through L ₂, because it is a high impedance branch compared with the turned on T ₁ branch. The sequential control strategy of inductive-CLCB is illustrated in Figure 7A. According to the strategy, the modelling process of inductance-CLCB will be developed as follows.

Assuming a short-circuit fault occurs at time t ₀ , the inductance-CLCB does not operation in this interval due to the delay in the detecting signal. As a result, the fault current follows the same path as in the normal condition.

Figure 7B shows the MOA-CLCB circuit, proposed by ABB (Mohammadi et al., 2021). It consists of two paths referred to as LCS and main breaker. Under normal conditions, the current is allowed to pass through the LCS path. However, while a short circuit fault occurs, all IGBTs in the main breaker path are turned on to force the fault current to pass through the main breaker, comprised of several identical modules paralleled with MOA. Once the main breaker establishes a conducting path, the UFD will be opened (Mohammadi et al., 2021). When the UFD complete open operation, all IGBTs in the main breaker path are turned off in the conventional switching strategy, and then the fault current is reduced to zero. However, this conventional switching strategy can result in a high voltage.

It is noted that the UFD is a special element with non-linear-time variable characteristics, which has two moving contactors. When the contactors begin to separate, the distance between the two contactors increases linearly with time (Skarby and Steiger, 2013; Hedayati and Jovcic, 2017). By utilizing this non-linear-time variable characteristic, a sequential switching strategy of IGBTs in the main breaker was proposed, as shown in Figure 7B. This strategy aims to reduce the peak fault current, overvoltage, and fault clearance time, and is referred to as sequential MOA-CLCB (Hedayati and Jovcic, 2018; Song et al., 2019).

At t ₀, a short circuit fault occurs, and the fault current flows through the LCS path. At t _d , let all IGBTs (T _m1∼T _mn ) in these sub-modules be turned on to form a new fault current path. During the interval [t _d , t ₁], the fault current commutates from the LCS path to the main breaker, and u _CLCB is about zero.

At t ₁ , let IGBT T _m1 be on to force the fault current to pass through MOA.1. Hence, u _CLCB is identical to the MOA.1 voltage, expressed as u C L C B t = u m o a . 1 , t 1 ≤ t < t 2 (19)

At t ₂ , T _m2 is turned on and u _CLCB (t) can be written as u C L C B t = u m o a . 1 + u m o a . 2 , t 2 ≤ t < t 3 (20)

The rest can be done in the same manner. Hence, the voltage u _CLCB across the sequential MOA-CLCB is written as a canonical form, such as u C L C B t = u m o a . 1   t 1 ≤ t < t 2 u m o a . 1 + u m o a . 2   t 2 ≤ t < t 3 ⋮ u m o a . 1 + u m o a . 2 + ⋯ + u m o a . n   t n ≤ t < t m (21)

Figure 7C shows the capacitance-CLCB circuit and its switching strategy [24]. At t ₀, the MTDC grid experiences a short circuit fault. At t _d , the MDTC grid detects the short circuit fault and sends a break command to capacitance-CLCB. Firstly, all IGBTs Tm in the main breaker branch is turned on to form the fault current transfer path. After that, the LCS branch receives the turn-off drive signal, and the UFD starts to open to commutate the fault current from the LCS branch to the main breaker. So, during the interval [t ₀ , t ₁], the voltage u _CLCB across the capacitance-CLCB is approximately equal to zero.

At t ₁, all IGBTs T _m is turned off, so that the fault current is forced to transfer to the capacitance C _m through freewheeling diodes D _m. So that C _m begins to be charged by the fault current, and the voltage across the capacitances starts to increase from its initial value of zero. Hence, the voltage u _CLCB is. u C L C B t = N C m ∫ t 1 t i F d t , t 1 ≤ t < t 2 (22)

Where N is the number of sub-modules in the main breaker.

At time t ₂, the voltage of C _m is charged to be equal to the rated voltage U _r of MOA, and the part of the fault current will pass through the MOA. Hence, the voltage u _CLCB (t) is u C L C B t = N U r + 1 C m ∫ t 2 t i F t − i m o a t d t t 2 ≤ t < t 3 (23)

At t ₃, the voltage of C _m is equal to the reference voltage U _ref of MOA, and MOA acts as a voltage source. Hence, the voltage u _CLCB is u C L C B t = N ⋅ U r e f   t 3 ≤ t < t c l e a r (24)

Based on above modelling process, the voltage u _CLCB (t) can be written as a united form as the followings u C L C B t = 0   t 0 ≤ t < t 1 N C m ∫ t 1 t i F d t   t 1 ≤ t < t 2 N U r + 1 C ∫ t 2 t i F t − i m o a t d t t 2 ≤ t < t 3 u C L C B t = N ⋅ U r e f   t 3 < t < t c l e a r (25)

In this section, the models of three typical CLCBs have been established, and the main contributions are the following. A canonical voltage source model, shown in Figure 6A, is proposed to describe the external electrical characteristic of the three typical CLCBs. The voltage source expressions are developed and shown in Eqs 18, 21, 25.

Although there are several types of CLCBs, a canonical voltage source model is established to describe their external electrical characteristics, as shown in Figure 6A. The difference lies in the fact that each type of CLCB has its own voltage source expression.

For example, assuming a short-circuit fault occurs at the middle position of the overhead line OL₁₂ between VSC₁ and VSC₂, the CLCB_a and CLCB_b will respond, but the other CLCBs still remain silent. By employing the aforementioned rule, a canonical RLC equivalent circuit of the DC grid with CLCB can be established and illustrated in Figure 9B. Compared with Figures 1A,B new voltage source, u _CLCBa , is inserted between node n₁ and the fault point n₀. It expresses that the CLCB_a connected with VSC1 has responded to the short circuit fault. And u _CLCBb is done in the same way as the CLCB_a.

The systematic formulation approach of the differential equation set developed in Section 2 is also suitable for writing the differential equation set for the canonical RLC equivalent circuit shown in Figure 9B. The systematic formulation of the differential equation set is a universal approach that is independent of the topology of the DC grid.

In the analysis of the circuit shown in Figure 9B, if we chose the loop current like that of Figure 1B, then the loop currents rector i , the capacitance voltages rector u and its current rector i _c are identical, also expressed by Eq. 1. Therefore, the incidence matrix A and R as well as L parameter matrix have an identical form. However, compared to Figure 1B, two new voltage sources u _CLCBa and u _CLCBb are added in Figure 9B. As a result, voltage source rector should be modified as u C L C B = u C L C B i b = 5 T = u C L C B a , u C L C B b , 0 , 0 , 0 b = 5 T (26) where u _CLCB1 = u _CLCBa ≠ 0 and u _CLCB2 = u _CLCBb ≠ 0, the CLCB_a and CLCB_b have responded since a short fault occured on the overhand line OL₁₂. Additionally, u _CLCB3 = u _CLCB4 = u _CLCB5 = 0, implying that the other CLCBs keep silent because no short fault has occurred on the overhead line OL₁₃, OL₂₄ and OL₃₄ illustrated in Figure 9A.

Hence, the differential equation set shown Eq. 7 can be modified as A × u = R × i + L × i ˙ + u C L C B u ˙ c = P × i (27)

This formula is called the normal form of the differential equation set, which will be used to calculate the short circuit fault current of DC grid with CLCB in this paper.

The normal form of differential equation set shares the following several merits.

1) The normal form is more general because it is independent of the DC grid’s topology and the SCPE categories.

This section will validate the short circuit fault current calculation method of the DC grid with CLCB proposed in Section 5 by employing the four-terminal DC grid shown in Figure 9A. The equivalent model of pole-to-ground short-circuit fault is illustrated in Figure 9B. The parameters of VSC are shown in Table 1. The equivalent inductance and equivalent resistance of the overhead line are 1 mH/km and 0.01 Ω/km respectively. The DC reactor at both ends of the overhead line is 150 mH. About the parameters of the three typical CLCBs: The rated voltage of a single MOA module for all three typical CLCBs is 40 kA. The sub-module capacitor of the Capacitance-CLCB is 240 uF. The coupling inductance pair of the Inductance-CLCB is 100 mH, and the coupling factor is 0.9.

In order to accurately calculate the short circuit fault current, the four-terminal DC grid with three different types of CLCB shown in Figure 9A is established in EMT simulation tool PSCAD. The simulation results are illustrated in Figure 10 by the solid lines and its VSC in this DC grid model is based on the EMT equivalent model of half-bridge MMC proposed in (CIGRE WG B4.57, 2014; Gnanarathna et al., 2011). This simulation tool is generally considered to have the ability to accurately estimate the performance of an HVDC grid in normal or fault conditions, making the EMT simulation results a reliable reference criterion. In short circuit fault current calculation, getting the fault current curves is the most concerned. Therefore, Figure 10 shows solely the fault current i _1F and i _2F curves. However, EMT simulation would require a lot of computing resources and be expensive and time-consuming.

In order to improve simulating efficiency, the short circuit fault current calculation equation is derived in Section 5 as expressed in Eq. 27. By applying the systematic formulation proposed in Section 2, the parameter matrices of the equivalent circuit shown in Figure 9B can be obtained. The incidence matrix A is also shown in Figure 2B, and Eq. 6 can be used to compute the P matrix. R and L matrices are R = R 1 + R 10 0 0 0 R 1 0 R 2 + R 20 R 2 0 0 0 R 2 R 2 + R 4 + R 24 R 4 0 0 0 R 4 R 3 + R 4 + R 34 − R 3 R 1 0 0 − R 3 R 1 + R 3 + R 13 L = L 1 + L 10 0 0 0 L 1 0 L 2 + L 20 L 2 0 0 0 L 2 L 2 + L 4 + L 24 L 4 0 0 0 L 4 L 3 + L 4 + L 34 − L 3 L 1 0 0 − L 3 L 1 + L 3 + L 13

Using the MATLAB program to solve the short circuit fault current calculation equation set Eq. 27, we can obtain the fault current i _1F and i _2F curves illustrated in Figure 10 by the dotted lines. For the inductance-CLCB, the formula of Eq. 18 is utilized to express u _CLCBa and u _CLCBb in the voltage source rector of Eq. 27, and the simulation results are shown in Figure 10A. The Eq. 21 and Eq. 25 are used to express the voltage source rector of MOA-CLCB and capacitance-CLCB, respectively, and the simulation results are shown in Figures 10B,C, respectively.

Figure 10 shows four curves labelled ①, ②, ③ and ④. The curve ① and ② are the fault current i _1F and i _2F, respectively. It can be observed that the simulated results from MATLAB, indicated by the dotted lines, almost agreed with that of conventional EMT simulation shown in the solid lines. The curves ③ and ④ are error curves, illustrating that the maximum computing error is less than 5%. Therefore, these results confirm that the proposed model and formulas are accurate enough to can meet the requirement of routine engineering analysis and design.

In order to verify that the accuracy of the proposed DC fault current fast-computing method is not affected by changes in test conditions, such as the location of fault occurrence, we selected a four-terminal DC network with an inductive CLCB as the test object, as shown in Figure 9. Several rounds of the general EMT simulation and the proposed DC fault current fast-computing method were performed respectively on PSCAD and MATLAB under the same test conditions. However, the fault location was selected as a variable. The compared errors between the EMT simulating results and the proposed method calculating results are shown in Figure 11. In this case, the 2-D graph shown in Figure 10 becomes a 3-D graph in Figure 11.

In these 3D graphs, the x-axis indicates the relative location of the short-circuit fault point, denoted as n_F, on the fault line. Let x be a ratio of L _fault/L _F-line, where L _fault represents the distance from the short circuit fault point n _F to VSC1, and L _F-line is the total length of the overhead line OL₁₂. The y-axis shows the time, and the vertical axes z shows the compared error between the proposed method and general EMT. Specifically, Figures 11A,B represent the errors fault current i _1F and i _2F, respectively. As shown in Figure 11, it can be observed that the maximum computing error is less than 5%, regardless of the location of the short circuit fault occurs on the line. Therefore, these results further confirm the accuracy of the proposed model and formulas with good stability and universality.

The simulation platform used in this paper was an AMD Ryzen7 4800H 2.90 GHz CPU with 16 GB of RAM and a 64-bit Windows 10 Operating System. The time step is 10 µs. For the PSCAD EMT simulation platform, it takes 0.9 s to start up. So, for the PSCAD EMT simulation and MATLAB calculation platform, let a dc short-circuit fault occurs at t = 1.0 s and fault time duration equals 10 ms. The time-consuming and efficiency improvements are listed in Table 2. It can be seen that the proposed short circuit current calculation method is much more efficient than the conventional EMT simulation and has relatively higher accuracy. The computing efficiency has been improved at least three hundred times, and the accuracy meets engineering analysis and design requirements.

At first, since ABB-DCCB is a typical hybrid DC circuit breaker and has been widely used in HVDC grids (Skarby and Steiger, 2013), it is applied to the four-terminal DC grid shown in Figure 9A. The EMT platform is utilized as a simulation tool to estimate its performance. The short circuit fault current simulation results are shown in Figure 12 by dotted lines, labelled as “i1F-DCCB” and “i2F-DCCB,” which is used as a reference criterion in this section.

In order to quickly compare the performance of the three typical CLCBs with the reference criterion, the proposed short circuit current calculation method is used to predict the fault currents. The simulation results are illustrated in Figures 12A–C by the solid lines, respectively.

According to Figure 12, it can be seen that the three typical CLCBs have a better fault current limiting ability than the conventional ABB-DCCB, and MOA-CLCB demonstrates the best performance. However, the other CLCBs take a longer fault isolation time than the conventional ABB-DCCB.

In the four-terminal DC network shown in Figure 9, the fault location n _F and normal current value are important parameters that will profoundly impact CLCB performance. Using the proposed short-circuit current calculation method, the performances of the three typical CLCBs can be estimated, and the simulation results are illustrated in Figure 13, which are three-dimensional graphs (3D graphs). The short-circuit fault current peak amplitude and fault isolation time of ABB-DCCB are also taken as standard values to evaluate the performance of the three typical CLCBs, such as peak fault current reduction value, peak current limiting ratio, and fault isolating time.

In these 3D graphs, the x-axis indicates the relative location of the short-circuit fault point n _F in the fault line. The y-axis shows the normal current, and the vertical axes z are the relative values of fault current peak amplitude, peak fault current limiting ratio and relative values of fault isolating time, respectively.

Figures 13A–C are the relative value of fault current peak amplitude, peak fault current limiting ratio and fault isolating time of the DC grid with MOA-CLCB, respectively. From Figure 13A, it can be observed that the relative value of the peak current amplitude depends on the fault point location and is almost independent of the normal value. However, the peak current limiting rate shown in Figure 13B is correlated with the fault point location and the normal value. As shown in Figure 13C, the isolating fault time of the MOA-CLCB is always shorter than that of ABB-DCCB. Consequently, MOA-CLCB demonstrates the best robustness performance among the three typical CLCBs.

Figures 13D–F demonstrate the performance of the capacitance-CLCB. The performance depends on both the short-circuit fault location and the normal value, but the short-circuit fault location has a more significant impact on the performance of capacitance-CLCB. When x > 0.8 and y < 0.5 kA, capacitance-CLCB will lose its current limiting ability.

Figures 13G–I show the performance of the inductance-CLCB, which is similar to that of the capacitance-CLCB. However, its current limiting effect is better than that of the capacitance-CLCB. It can be observed that there exists an optimal current limiting area, x < 0.3. In this area, the peak current limit rate exceeds 40%, and the relative value of peak current is greater than 5 kA. So, its current limiting effect is far better than the other two CLCBs in the optimal current limiting area. However, it is important to note that the inductance-CLCB achieves its best current limiting effect at the expense of a longer fault isolating time.