AUTHOR=Hosseinzadeh Shima , Biglari Mehrdad , Fey Dietmar 

TITLE=TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms

JOURNAL=Frontiers in Nanotechnology

VOLUME=Volume 3 - 2021

YEAR=2021

URL=https://www.frontiersin.org/journals/nanotechnology/articles/10.3389/fnano.2021.765947

DOI=10.3389/fnano.2021.765947

ISSN=2673-3013

ABSTRACT=Non-volatile memory (NVM) technologies offer number of advantages over conventional memory technologies such as SRAM and DRAM. These include a smaller area requirement, a lower energy requirement for reading and partly for writing, too, of course the non-volatility and especially the qualitative advantage of multi-bit capability. It is expected that memristors based on ReRAMs, PCMs or STT-MRAMs will replace conventional memory technologies in certain areas or complement them in hybrid solutions.
To support the design of systems that use NVMs, there is still research to be done on the modeling side of NVMs. In this paper, we focus on multi-bit ternary memories in particular. Ternary NVMs allow the implementation of extremely memory-efficient ternary weights in neural networks, which have sufficiently high accuracy in interference, or they are part of carry-free fast ternary adders. Furthermore we lay a focus on the technology side of memristive ReRAMs. In this paper, a novel memory model in circuit-level is presented to support the design of systems that profit from ternary data representations. This model considers two read methods of ternary ReRAMs, namely serial read and parallel read. They are extensively studied and compared in this work, as well as write-verification method which is often-used in NVMs to reduce device stress and to increase the endurance. In addition, a comprehensive tool for the ternary model was developed which is capable of performing energy, performance, and area estimation for a given set-up. In this work, three case studies were conducted namely, area cost per trit, excessive parameter selection for the write-verification method, and the assessment of pulse widths variation and their energy-latency trade-off for write-verification in ReRAM.