AUTHOR=Linares-Barranco Bernabe , Serrano-Gotarredona Teresa , Camuñas-Mesa Luis A., Perez-Carrasco Jose A., Zamarreño-Ramos Carlos , Masquelier Timothee 

TITLE=On Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex

JOURNAL=Frontiers in Neuroscience

VOLUME=volume 5 - 2011

YEAR=2011

URL=https://www.frontiersin.org/journals/neuroscience/articles/10.3389/fnins.2011.00026

DOI=10.3389/fnins.2011.00026

ISSN=1662-453X

ABSTRACT=In this paper we present a very exciting overlap between emergent nano technology
and neuroscience. We are linking one type of memristor nano technology devices to the biological synaptic update
rule known as Spike-Time-Dependent-Plasticity found in real biological synapses.
Understanding this link allows neuromorphic engineers to develop circuit architectures
that use this type of memristors to artificially emulate parts of the visual cortex. 
We focus on the type of memristors referred to as voltage driven memristors and
focus our discussions on a behavioral macro model for such devices.
The implementations
result in fully asynchronous architectures with neurons sending their action potentials not
only forwards but also backwards. One critical
aspect is to use neurons that generate spikes of specific shapes. By changing the shapes of the neuron action potential spikes we can tune and manipulate
the STDP learning rules for both excitatory and inhibitory synapses. We show how
neurons and memristors can be interconnected to achieve large scale spiking learning systems,
that follow a type of multiplicative STDP learning rule. We briefly extend the architectures
to use three-terminal transistors with similar memristive behavior.
We illustrate how a V1 visual cortex layer can assembled and how it is
capable of learning to extract orientations from visual data coming from a real artificial
CMOS spiking retina observing real life scenes. Finally, we discuss limitations
of currently available memristors.
The results presented are based on behavioral simulations and do not take into
account non-idealities of devices and interconnects. The aim of this paper is to present, in
a tutorial manner, an
initial framework for the possible development of fully asynchronous STDP learning neuromorphic architectures
exploiting two or three terminal memristive type devices. All files used for the simulations are made available through the journal web site.