AUTHOR=Scholze Stefan , Schiefer Stefan , Partzsch Johannes , Hartmann Stephan , Mayr Christian G., Höppner Sebastian , Eisenreich Holger , Henker Stephan , Vogginger Bernhard , Schüffny Rene TITLE=VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality JOURNAL=Frontiers in Neuroscience VOLUME=5 YEAR=2011 URL=https://www.frontiersin.org/journals/neuroscience/articles/10.3389/fnins.2011.00117 DOI=10.3389/fnins.2011.00117 ISSN=1662-453X ABSTRACT=

State-of-the-art large-scale neuromorphic systems require sophisticated spike event communication between units of the neural network. We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an field programmable gate arrays (FPGA)-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike-based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behavior of neuromorphic benchmarks. The specialized, dedicated address-event-representation communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based pulse channel, which transmits configuration data at the full bandwidth otherwise used for pulse transmission. The overall so-called pulse communication subgroup (ICs and FPGA) delivers a factor 25–50 more event transmission rate than other current neuromorphic communication infrastructures.