AUTHOR=Guo Liyuan , Weiße Annika , Zeinolabedin Seyed Mohammad Ali , Schüffny Franz Marcus , Stolba Marco , Ma Qier , Wang Zhuo , Scholze Stefan , Dixius Andreas , Berthel Marc , Partzsch Johannes , Walter Dennis , Ellguth Georg , Höppner Sebastian , George Richard , Mayr Christian 

TITLE=68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOI

JOURNAL=Frontiers in Neuroscience

VOLUME=Volume 18 - 2024

YEAR=2024

URL=https://www.frontiersin.org/journals/neuroscience/articles/10.3389/fnins.2024.1432750

DOI=10.3389/fnins.2024.1432750

ISSN=1662-453X

ABSTRACT=IntroductionMulti-channel electrophysiology systems for recording of neuronal activity face significant data throughput limitations, hampering real-time, data-informed experiments. These limitations impact both experimental neurobiology research and next-generation neuroprosthetics.MethodsWe present a novel solution that leverages the high integration density of 22nm fully-depleted silicon-on-insulator technology to address these challenges. The proposed highly integrated programmable System-on-Chip (SoC) comprises 68-channel 0.41 μW/Ch recording frontends, spike detectors, 16-channel 0.87–4.39 μW/Ch action potentials and 8-channel 0.32 μW/Ch local field potential codecs, as well as a multiply-accumulate-assisted power-efficient processor operating at 25 MHz (5.19 μW/MHz). The system supports on-chip training processes for compression, training, and inference for neural spike sorting. The spike sorting achieves an average accuracy of 91.48 or 94.12% depending on the utilized features. The proposed programmable SoC is optimized for reduced area (9 mm2) and power. On-chip processing and compression capabilities free up the data bottlenecks in data transmission (up to 91% space saving ratio), and moreover enable a fully autonomous yet flexible processor-driven operation.DiscussionCombined, these design considerations overcome data-bottlenecks by allowing on-chip feature extraction and subsequent compression.