CdSe nanowires were grown in a vertical array through gold-catalyzed chemical vapor deposition, as described elsewhere, [27] and were then dispersed in alcohol and drop cast onto a Si/SiO₂ chip, which consists of Si substrate coated with a 300-nm thick SiO₂ layer. After CdSe nanowires were dispersed onto a chip, a thin poly-methyl methacrylate (PMMA) layer was spin coated onto the chip, followed by electron-beam lithography to open channels at a nanowire's ends. Exposed PMMA was removed by developing the chip. Afterwards, the chip was transferred to a thermal evaporator (Cressington-308R) for indium metallization (30 nm), followed by lift-off in acetone to obtain a finished device. The other indium wire end was bonded to a large gold pad used for placement of a gold-coated electrical probe. The samples were air stabilized for at least a week prior to testing.

Optical gating through P_g(λ_g) has two basic control parameters: wavelength, λ_g, and power level, P_g, under one-beam CW operation, but it can be readily extended to other operation modes. For instance, multiple independent beams and pulsed illumination may be represented as P_g(λ_g1, λ_g2,…,λ_gN) and P_g(t, λ_g1, λ_g2,…,λ_gN), respectively. We fully characterize LET output and transfer characteristics under one-beam CW operation with two illumination conditions: (i) illuminating the center of the SNW with a focused CW laser (“focused illumination”) with an optical diffraction-limited spot size at wavelengths of 633, 532, 442, or 325 nm; and (ii) illuminating the LET uniformly with “white light” from a halogen lamp (“uniform illumination”).

The novel LET concept requires performance metrics for evaluation and comparison against FETs; thus, FET figures of merit are adapted, such as the two important input-output relationships: (i) “output characteristics” or I_ds vs. V_ds under a constant illumination condition P_g(λ_g), which is equivalent to the FET's output characteristic under a constant gate voltage V_g; and (ii) “transfer characteristics” or I_ds vs. P_g(λ_g) under a constant V_ds, which is equivalent to a FET's I_ds vs. V_g under a constant V_ds. A FET's gate voltage, V_g, is replaced by a LET's gate power P_g(λ_g), which not only serves the same function of modulating S-D conductivity but also offers an avenue to achieve novel functions beyond those in a FET. Characteristic (i) is shared by both LET and photo-detection applications, while characteristic (ii) is required for LETs and FETs as a measure of turn-on energy, and in particular, for LETs to realize novel functions.

I_ds vs. V_ds measurements were collected with a Keithley® 2401 low voltage sourcemeter® that was remotely operated with LabTracer v2.9 software via a GPIB connection. For currents below ~1 nA, a Stanford Research System SR570 current pre-amplifier was used in conjunction with the Keithley®. Illumination sources consisted of halogen light, 532, 441.6, and 325 nm lasers ported through a Horiba LabRAM HR800 confocal Raman system with an internal 632.8 nm laser. Due to limited probe spacing for electrical measurements, all illumination sources were focused through a 50x long working distance (LWD) objective lens (N.A. = 0.50), except 325 nm, which went through a 10x MPLAN objective lens (N.A. = 0.25). Laser powers were limited to absolute powers of ~3 μW, as measured on the sample side of the microscope lens, to avoid potential laser-induced material modifications. Laser powers were altered through a combination of a standard neutral density filter in the Raman system and an adjustable neutral density filter in the laser path. Laser powers were measured with a Thor Labs PM100D power meter, and six and ten averaged measurements were used for D1 and D2, respectively, to calculate average powers. The total power of the halogen light was estimated to be 69.1 μW.

The laser spot size is estimated by the optical diffraction limit formula 1.22λ/N.A., where N.A. is the numerical aperture of the microscope lens. The fraction of the laser power actually absorbed is estimated by taking the ratio of the nanowire diameter to the laser spot size. The estimated ratios for the 632.8, 532, 441.6, and 325 nm lasers are 5.18, 6.16, 7.43, and 10.1% for a nanowire with an 80 nm diameter (device D1). For halogen illumination, the fraction of actual absorbed light is estimated using the ratio of the nanowire's cross section to the total illumination area. For the 50x LWD (10x MPLAN) objective lens, the illumination area is ~279 (~1450) μm². The ratio for the 80 nm wide/10 μm long nanowire (D1) is ~3.2 10⁻⁶, and the power estimation for light actually absorbed is ~0.22 μW (which is comparable to that for the focused laser beam). All the illumination powers mentioned in the manuscript were applied powers, unless an actually absorbed power was explicitly stated.

Figure 2 provides material and device characteristics. Figure 2A displays an SEM image of a 10-μm-long CdSe SNW (device 1 or D1) with indium (In) contacts forming M-S junctions at each end. The uniform single-crystalline CdSe SNW was grown in wurtzite phase along the [0001] axis with a diameter of ~80 nm, as revealed by the low magnification transmission electron microscopy (TEM) image in Figure 2B, with the selected area diffraction pattern (SADP) as inset, and Figure 2C's high-resolution TEM (HRTEM) image showing a 0.69 nm inter-planar spacing. The gold catalyst at the SNW end (Figure 2B) suggests the vapor-liquid-solid growth mechanism [29]. The CdSe-SNW's laser-power-dependent photoluminescence (PL), Figure 2D, shows a strong emission peak at 1.78 eV that matches CdSe's bandgap energy [30]. The inset overlays a PL map upon an optical image to demonstrate relatively homogenous SNW emission, and by extension, homogenous material quality across the SNW channel. In Figure 2E, the output characteristic, S-D current I_ds vs. S-D voltage V_ds, is demonstrated for the device with and without light illumination using a halogen light, where illumination optically modulates or “gates” the electrical conductivity between dark (“off”) and illuminated (“on”) states. The I_ds vs. V_ds curves for these two states clearly resembles those of a FET's off and on states [1], respectively, especially when V_ds < ~7 V.

Results for two devices, device 1 (D1) and device 2 (D2) with lengths of ~10 and ~5.5 μm and similar diameters (~80 nm), are presented to illustrate general LET properties, and to demonstrate the potential for characteristic tuning and optimization. The two devices were fabricated in essentially the same way.

Device dark currents reveal negligible reverse bias current and rectification (diode-like behavior) under forward bias, e.g., Figure 2E. LET operation occurs under forward bias for both devices. Rectification is indicative of asymmetric In/CdSe contacts for both devices, where one M-S junction is close to ohmic and the other forms a Schottky contact [31]; large asymmetric contacts are desired as they drastically reduce the dark current or off state and thereby improve the on/off ratio. The Schottky barrier largely determines the turn-on voltage, V_{D, on}, which is ~8 V for D1 and >21 V for D2. For instance, D2 shows nearly resistive behavior up to V_ds = 21 V with I_ds reaching only ~15 pA, compared to D1's range from ~1 nA to ~4 μA over 1–21 V. The vast difference between the two devices might stem from a thin SeO_x layer (x = 2–3) [32] at the In/CdSe junction, although the details require further study. These results hint that dark or off state parameters can be controlled through M-S contact engineering.

Representative LET output characteristics are shown in Figures 3A–D for D1 and in Figures 3E,F for D2, respectively, to exemplify how LET performance depends on the gate power/wavelength, illumination condition, and device variation. D1 exhibits two well-separated plateaus, respectively, starting at V_ds ~ 4–5 and ~14–18 V depending on the gate wavelength and power. For example, the second plateau's onset is at ~14–15 V for 633 nm illumination but shifts to ~16–18 V under 442 nm excitation. Two tunable plateaus can potentially offer two distinct, customizable on states. For D2, the first and second plateau are comparatively not well separated, and both 532 nm and halogen illumination have their first plateau at ~2 V with respective power-dependent, second plateaus at ~6–7.5 V (532 nm) and ~5–5.75 V (halogen). Each plateau appears at respectively lower V_ds values than in D1, and because of the extremely low dark current, the long second plateau extends to the highest V_ds measured. For D1, the maximum on/off ratios typically occur at V_ds < 5 V, and vary from 10² to 10⁴ depending on the gate power and wavelength. For instance, Figure 3B contains on/off ratios of ~5 × 10⁴ and ~2 × 10⁴ at V_ds = 1.43 and 4.95 V, respectively, when P_g(532 nm) ≈ 2 μW. The on/off ratios for D2 in Figure 3E are ~1.0 × 10⁶ and ~1.1 × 10⁶ at V_ds = 1.43 and 4.95 V when P_g(532 nm) ≈ 2.6 μW. When P_g(halogen) ≈ 69 μW in Figure 3F, the on/off ratios are ~6 × 10⁵ and ~1 × 10⁶ at V_ds = 1.43 and 4.95 V, respectively.

Differences between D1 and D2 indicate that a LET's characteristics may be tuned and optimized through material and device engineering. A large M-SNW contact barrier is generally desirable for producing small off state currents over the operation range, and can be optimized to maximize the on/off ratio. Note that current levels for different “gate” wavelengths in Figures 3A–D showed considerable variations, which is fundamentally due to wavelength-dependent light-matter interaction effects, e.g., absorption and carrier dynamics, and illumination conditions, e.g., power density and beam size. This feature offers the unique LET advantage of flexibility in achieving gate functions compared to FETs.

The transfer characteristics allow extraction of several performance metrics. A FET's threshold gate voltage, V_T, and subthreshold swing, S, are respectively defined as the onset of a linear region in the I_ds − V_g curve (i.e., voltage-controlled resistor behavior), and as the inverse linear slope on a semi-log I_ds − V_g plot [4]. Their physical interpretations, respectively, are the gate voltage required for device operation and the gate voltage increment to induce an order of magnitude current change below V_T. A small S-value implies a small energy or power consumption to turn on or operate a FET. Figure 4 contains D1's and D2's transfer characteristics, which in general, resemble a FET's transfer characteristics, e.g., increasing I_ds as the gate power P_g increases under constant V_ds, except a LET replaces V_g with P_g. A LET's threshold gate power, P_T, then, corresponds to the onset of a linear I_ds − P_g region for a given λ_g, and S_LET is its subthreshold swing. Significantly, FETs usually do not operate in the “subthreshold swing” region, while a LET can employ this range to realize optical logic gates and for an interesting optical amplification effect. Taking D2's I_ds vs. P_g curves, Figure 4E, with λ_g = 532 nm as examples, typical P_T and S_LET values at V_ds = 1.43 (4.98) V are, respectively, ~30. (~30.) nW, and ~2.8 (~2.5) nW/decade. For reference, advanced FETs have respective V_T and S parameters of 100–200 mV, and ~70–90 mV/decade [33]. At V_ds = 1.43 V, P_g = 0.11 μW yields I_ds ≈ 0.35 μA, and a LET dynamic power consumption of ~0.5 μW, which is comparable to advanced FETs [34]. A LET's off-state energy consumption can be very low. For instance, the dark current is ~1 pA at V_ds = 1.43 V with a corresponding off power consumption of ~1.5 pW, which is lower than a FET of similar length [34]. Switching energy, or the amount of energy needed to go from off to on states, is a frequently quoted metric. Our current measurement system prevented a direct measurement of the switching time, although it may be reasoned that LETs can have lower switching energies than modern FETs. Note that a LET may be viewed as a FET without the gate, which means that a LET's switching time is limited by the carrier transit time rather than a FET's capacitive delay. Most direct band gap semiconductors possess room temperature carrier lifetimes on the order of 100 ps without an applied bias, where applying a bias, especially for a short conducting channel length, reduces the transit time by more quickly wiping out free carriers. Simple estimates based on D2's performance support lower switching energies in LETs. For example, even an assumed 100 ps delay time would yield a switching energy of 0.05 fJ/switch (0.5 μW × 100 ps) associated with the S-D current, and 0.01 fJ/switch (0.1 μW × 100 ps) from the optical gating action, which yields a total switching energy less than typical FET values of 0.1–1.0 fJ/switch [35]. The switching energy could be further reduced by reducing the channel length and optimizing the contacts.

LET transfer characteristics are used to illustrate the underlying principles for a few important applications. D2's 532 nm illumination characteristics, Figure 4E, are re-plotted on a double log scale in Figure 5A, with only V_ds = 1.43 and 4.98 V shown for clarity, to more clearly portray the three major operating regions: super-linear (dark gray region), linear (medium gray), and sublinear/saturation (light gray). Different regions can offer different unique applications, as the examples highlighted below.

Complementary to the above mentioned functions, LETs can also be used as a differentiator under zero or low P_g, and as a phase tuner as P_g is increased. Figure 5H shows the I_ds(t) vs. V_ds(t) curves for different P_g values, where V_ds(t) is a sine wave modulation with an amplitude of 5.0 V and a DC offset to remove the negative portion. The I_ds(t) curve exhibits a 90° phase delay with respect to V_ds(t) when P_g = 0, which indicates that the device functions as a differentiator by converting a sine wave into a cosine wave; increasing P_g results in a tunable phase shift that gradually approaches zero, e.g., at P_g = 2.6 μW. This effect can be understood as changing the LET's impedance by varying the gate power.

The I_ds − V_ds curves in Figure 3 may be understood qualitatively with the photo-conductivity model proposed by Mott and Gurney [22]. The first plateau could be associated with the “primary photoconductivity” which produces current as a result of photo-generated electrons and holes flowing through the nanowire under applied bias. A steady state condition is formed when just enough external carriers entering the nanowire through the electrodes replenish those leaving the device. Under single point illumination, the collection efficiency, Ψ, can be approximately described by: (1)ψ=w/L(1−e−x0/w), where w is the carrier's mean free path (which is proportional to the applied field), L is the nanowire's length, and x₀ is the illumination site measured from the anode (cathode) when the carriers are electrons (holes). This theory suggests a continuous photocurrent increase from V_ds = 0 until saturation at a sufficiently large V_ds to produce w >> L and Ψ → 0.5 (see Figure A5 in Supplementary Material for simulated Ψ vs. V_ds curves). Under uniform illumination, the collection efficiency is then: (2)ψ=w/L[1−w/L(1−e−L/w)].

If all photons are absorbed, the sum of the collection efficiencies of both electrons and holes will yield a quantum efficiency, η_QE, defined as I_ph/(eN_ph), where I_ph is the photo-induced current, and N_ph is the number of absorbed photons. When current saturation occurs, η_QE = 100%. For instance, absorbing 2 μW of 620 nm light with η_QE = 100% yields a 1 μA current. As V_ds approaches V_{D, on}, a major Schottky barrier reduction [31, 39] allows excess carriers to enter the nanowire through the electrodes, which then produce a drastic I_ds increase that allows η_QE >> 1. The detailed operation mechanism is likely much more complex than that described by the simple photoconductive mode, and deserves further investigation.

Significantly, the collection efficiency is expected to improve drastically at low V_ds with nanometer-length devices (Figure A5 in Supplementary Material), which should further reduce the static power consumption and provide lower V_ds than those demonstrated here. The maximum applied laser power is about 3 μW and corresponds to a power density of ~0.60 W/mm², which is less than that delivered by an efficient light-emitting diode [40]. The gate power actually used is only about 10% of the applied power because the laser spot size is considerably larger than the nanowire diameter (see Section Materials and Methods for energy loss estimates). Reducing the beam size closer to the SNW's diameter could reduce P_g by at least a factor of 10 [41], and as is well established in FET devices, reducing the channel length can further reduce the required V_ds (Figure A5 in Supplementary Material). Enhanced efficiency and reduced energy consumption could significantly reduce thermal issues plaguing nanoscale FET-containing electronics devices. We note that FETs posses a thermal dynamic limit of S ≥ (kT/q) ln(10) = 60 mV/decade at 300 K, whereas for LETs, S_LET is extrinsic in nature through its dependence of w on the carrier density, which in turn depends on the defect density. Thus, S_LET can be significantly improved by shortening the conduction channel, perfecting the material quality, and by choosing materials with strong absorption.

LETs are also capable of quantum scale operation. A LET's structural simplicity removes potential obstacles that FETs face for further down scaling. A LET shares the same limit of a FET, that is, the nanostructure dimensions practically achievable, e.g., 1–7 nm for Si nanowires [42], but LETs do not require complex and sophisticated fabrication steps for physical gates and doping. In general, ballistic transport theory suggests that commercially viable currents could be achieved in quantum structures [43]. Quantum conductance, which limits 1-D ballistic transport, is given by G = nG₀, where G₀ = 2e²/h is the minimum conductance and n are integers representing quantized energy levels. This equation [44] yields a maximum quantum impedance for the conducting channel of Z₀ = 1/G₀ = 12.9 kΩ. The on-state energy consumption could be as low as ~13 nW/LET when I_ds = 1 μA, and the required minimal V_ds would only be 13 mV (not including the voltage drop over the S/M junctions). Given the highly localized nature of the 1-D energy density of states, LET conductivity is expected to be quantized, and thus, tunable using different photon energies.

Industry may employ at least two basic illumination modes in an integrated LET circuit depending on the application: (i) uniform, broad-area illumination over a high-density LET array with SNWs, or (ii) separated light beams directed to individual or small groups of LETs through, for instance, sharp fiber tips or nanoscale emitters embedded on the same chip. For either mode, multiple light sources of the same or different wavelength(s) and/or intensities can be combined into one beam but controlled independently.

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.