Research Topic

Integration of III-V Compound Semiconductors on Silicon Platform

About this Research Topic

There has been a surge on the integration of III-V-based semiconductor materials and devices on silicon to overcome the limitations in Moore's law and to address the exponential data traffic growth. The integration strategy effectively leverages the strength of high-performance III-V optoelectronic devices and well-established silicon microelectronics and photonics platforms. While photonic integrated circuits have been demonstrated by heterogeneous integration, relying on the bonding technologies, the monolithic integration approach by heteroepitaxy is also seeing advances in both material perfection and various optoelectronic device implementation. In this Research Topic, we would like to collect recent developments and comprehensive overviews in both material study and device physics investigation in the field of III-V and III-Nitride semiconductors integrated on silicon.

As mentioned above, the integration of III-Vs on silicon exhibits great potentials in realizing high speed and efficient optoelectronic devices with cost-effective and massive-production capability. However, regarding the two mainstream integration approaches, i.e. heterogeneous and monolithic integrations, there are some issues to be explored. For the heterogeneous integration based on bonding technologies, although we are stepping into a circuit level, it is appealing to further increase the integration density by downsizing the device footprints. Their bandwidth limit, co-packaging solution, and losses in the optical interconnect require a continuous endeavor. Another important consideration is to demonstrate complementary metal-oxide-semiconductor (CMOS)-manufacturable ability without limiting to III-V substrate sizes. Some novel approaches, namely bonded template growth and micro-transfer printing, are targeting to address this challenge. For the monolithic integration method by heteroepitaxy, the most critical and urgent requirement is to minimize the dislocations arising from the lattice, thermal, and polarity mismatches between III-Vs and silicon. Only by perfecting the buffer materials can the device's performance and reliability get improved. Thermal budget, buffer thickness, and stress control need to be tackled towards high volume production. Recent progress in effective dislocation filters and selective area heteroepitaxy demonstrate promise to resolve the challenges in monolithic integration.

The scope of this Research Topic will cover material growth, device, and circuit design, fabrication, and measurement. Topics can include:

1. Hybrid integration of III-V and III-Nitride materials on a silicon platform
2. Fabrication and characterization of electronic and photonic devices on silicon by heterogeneous integration
3. Blanket heteroepitaxy and selective area heteroepitaxy of III-V and III-Nitride semiconductors on silicon or silicon-on-insulator
4. Design and modeling of coupling between III-V photonic devices with silicon photonic components
5. III-V micro- and nano-structures integrated on silicon or silicon-on-insulator
6. Interface and strain study for III-V integrated on silicon
7. Silicon-based photonics-electronics convergent circuits
8. Theoretical and experimental study of novel integration schemes


Keywords: monolithic integration, heterogeneous integration, silicon photonics, optoelectronics, heteroepitaxy, bonding


Important Note: All contributions to this Research Topic must be within the scope of the section and journal to which they are submitted, as defined in their mission statements. Frontiers reserves the right to guide an out-of-scope manuscript to a more suitable section or journal at any stage of peer review.

There has been a surge on the integration of III-V-based semiconductor materials and devices on silicon to overcome the limitations in Moore's law and to address the exponential data traffic growth. The integration strategy effectively leverages the strength of high-performance III-V optoelectronic devices and well-established silicon microelectronics and photonics platforms. While photonic integrated circuits have been demonstrated by heterogeneous integration, relying on the bonding technologies, the monolithic integration approach by heteroepitaxy is also seeing advances in both material perfection and various optoelectronic device implementation. In this Research Topic, we would like to collect recent developments and comprehensive overviews in both material study and device physics investigation in the field of III-V and III-Nitride semiconductors integrated on silicon.

As mentioned above, the integration of III-Vs on silicon exhibits great potentials in realizing high speed and efficient optoelectronic devices with cost-effective and massive-production capability. However, regarding the two mainstream integration approaches, i.e. heterogeneous and monolithic integrations, there are some issues to be explored. For the heterogeneous integration based on bonding technologies, although we are stepping into a circuit level, it is appealing to further increase the integration density by downsizing the device footprints. Their bandwidth limit, co-packaging solution, and losses in the optical interconnect require a continuous endeavor. Another important consideration is to demonstrate complementary metal-oxide-semiconductor (CMOS)-manufacturable ability without limiting to III-V substrate sizes. Some novel approaches, namely bonded template growth and micro-transfer printing, are targeting to address this challenge. For the monolithic integration method by heteroepitaxy, the most critical and urgent requirement is to minimize the dislocations arising from the lattice, thermal, and polarity mismatches between III-Vs and silicon. Only by perfecting the buffer materials can the device's performance and reliability get improved. Thermal budget, buffer thickness, and stress control need to be tackled towards high volume production. Recent progress in effective dislocation filters and selective area heteroepitaxy demonstrate promise to resolve the challenges in monolithic integration.

The scope of this Research Topic will cover material growth, device, and circuit design, fabrication, and measurement. Topics can include:

1. Hybrid integration of III-V and III-Nitride materials on a silicon platform
2. Fabrication and characterization of electronic and photonic devices on silicon by heterogeneous integration
3. Blanket heteroepitaxy and selective area heteroepitaxy of III-V and III-Nitride semiconductors on silicon or silicon-on-insulator
4. Design and modeling of coupling between III-V photonic devices with silicon photonic components
5. III-V micro- and nano-structures integrated on silicon or silicon-on-insulator
6. Interface and strain study for III-V integrated on silicon
7. Silicon-based photonics-electronics convergent circuits
8. Theoretical and experimental study of novel integration schemes


Keywords: monolithic integration, heterogeneous integration, silicon photonics, optoelectronics, heteroepitaxy, bonding


Important Note: All contributions to this Research Topic must be within the scope of the section and journal to which they are submitted, as defined in their mission statements. Frontiers reserves the right to guide an out-of-scope manuscript to a more suitable section or journal at any stage of peer review.

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Submission Deadlines

11 September 2021 Manuscript

Participating Journals

Manuscripts can be submitted to this Research Topic via the following journals:

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Topic Editors

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Submission Deadlines

11 September 2021 Manuscript

Participating Journals

Manuscripts can be submitted to this Research Topic via the following journals:

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