Bio-plausible learning in neuromorphic electronics based on emerging memory devices

Neuromorphic electronics based on in-memory computing promise energy-efficient, adaptive intelligence by leveraging the native physics of nanoscale emerging devices. Yet a critical frontier remains: robust, lifelong on-chip learning that continuously adapts to non-stationary data without catastrophic forgetting. Current efforts in semiconductor R&D are largely focused on device-level emulations of synaptic and neural functions, hardware-informed spiking neural networks (SNN) simulations, and small-scale prototypes of local learning rules like STDP. However, while STDP-based systems offer promising performance in tasks like pattern detection, they often struggle with scalability to deep SNNs and fail to address the stability-plasticity dilemma in dynamic environments. To bridge this gap, bio-plausible mechanisms such as eligibility traces, meta-plasticity, and three-factor learning rules provide a pathway toward more robust and possibly hardware-friendly implementations. Therefore, breakthroughs are needed in co-design frameworks that (1) map bio-plausible plasticity to device/circuit dynamics, (2) validate scalability via hardware-aware simulations and demonstrators, and (3) quantify system-level trade-offs.

This Research Topic explores the intersection of emerging nanodevice physics, neuromorphic circuit architectures, and computational neuroscience to enable energy-efficient on-chip learning at the edge. The field now requires a transition from software emulation to physical hardware where device dynamics directly implement adaptation. We encourage exploratory studies on leveraging the unique properties of emerging memory technologies to realize bio-plausible synaptic and neuronal dynamics across multiple timescales. We seek learning strategies that remain stable while leveraging device non-idealities to address the stability-plasticity dilemma during continual operation.

We welcome papers addressing:

- Device physics for learning primitives: Mechanisms where synaptic plasticity and neuronal adaptation emerge from the intrinsic physics of novel memory devices (e.g., thin-film and 2D materials enabling memresistive or memcapacitive switching). We prioritize work on multi-timescale dynamics, analog state programming and retention, and strategies that either mitigate or exploit non-idealities (stochasticity, nonlinearity, variability, drift, limited endurance) as computational resources for probabilistic or energy-efficient adaptation.

- Circuit architectures for bio-plausible adaptation: Analog and mixed-signal designs that physically implement advanced learning rules (reward-modulated STDP, three-factor rules, predictive coding) within hardware constraints. Contributions should demonstrate how circuit dynamics embody these rules in emerging memresistive, memcapacitive, or hybrid platforms, validated through prototypes that maintain stability amidst variability.

- Software-hardware co-design for efficient learning & computing: Joint optimization of SNN models, learning algorithms, and physical device characteristics. Topics include credit assignment in physical networks, device physics for novel computational and learning primitives at the synapse and neuron levels, multi-timescale dynamics enabled by hardware physics, strategies to prevent catastrophic forgetting in mixed-signal architectures and digital-twin approaches designed to close the gap between simulations and hardware demonstrators for scalable deployment.

- Neuromorphic prototypes and demonstrators: Experimental validation of on-chip learning in neuromorphic chips based on in-memory computing. In that scope we seek rigorous metrics, datasets, and protocols for evaluating on-chip learning under closed-loop, event-based, and non-stationary conditions. While baseline static classification (e.g., MNIST/CIFAR) is accepted for validation, we strongly encourage benchmarks involving time-dependent, noisy datasets representative of realistic scenarios (e.g., DVS streams, EMG, EEG, robotic control).

We also encourage studies addressing fundamental trade-offs affecting performance, including update precision vs endurance, variability tolerance vs control electronics overhead, scalability vs device-to-device variability, and biological plausibility vs hardware efficiency. We welcome research that define the limits of physical learning, offering rigorous analysis of where specific device physics constrain or enable scalable continual adaptation. Strong contributions will demonstrate how device physics, circuit design, and computational neuroscience can be co-optimized to enable learning that is biologically grounded, energy-efficient, and physically realizable, with scalability and system-level implications assessed through hardware-aware modeling and simulation.