Enabling technologies for very large-scale synaptic electronics

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Background

An important part of the colossal effort associated with the understanding of the brain involves using electronics hardware technology in order to reproduce biological behavior in ‘silico’. The idea revolves around leveraging decades of experience in the electronics industry as well as new biological findings that are employed towards reproducing key behaviors of fundamental elements of the brain (notably neurons and synapses) at far greater speed-scale products than any software-only implementation can achieve for the given level of modelling detail.

So far, the field of neuromorphic engineering has proven itself as a major source of innovation towards the ‘silicon brain’ goal, with the methods employed by its community largely focused on circuit design (analogue, digital and mixed signal) and standard, commercial, Complementary Metal-Oxide Silicon (CMOS) technology as the preferred `tools of choice’ when trying to simulate or emulate biological behavior. However, alongside the circuit-oriented sector of the community there exists another community developing new electronic technologies with the express aim of creating advanced devices, beyond the capabilities of CMOS, that can intrinsically simulate neuron- or synapse-like behavior. A notable example concerns nanoelectronic devices responding to well-defined input signals by suitably changing their internal state (‘weight’), thereby exhibiting `synapse-like’ plasticity. This is in stark contrast to circuit-oriented approaches where the `synaptic weight’ variable has to be first stored, typically as charge on a capacitor or digitally, and then appropriately changed via complicated circuitry.

The shift of very much complexity from circuitry to devices could potentially be a major enabling factor for very-large scale `synaptic electronics’, particularly if the new devices can be operated at much lower power budgets than their corresponding 'traditional' circuit replacements. To bring this promise to fruition, synergy between the well-established practices of the circuit-oriented approach and the vastness of possibilities opened by the advent of novel nanoelectronic devices with rich internal dynamics is absolutely essential and will create the opportunity for radical innovation in both fields. The result of such synergy can be of potentially staggering impact to the progress of our efforts to both simulate the brain and ultimately understand it.

In this research topic, we wish to provide an overview of what constitutes state-of-the-art in terms of enabling technologies for very large scale synaptic electronics, with particular stress on innovative nanoelectronic devices and circuit/system design techniques that can facilitate the development of very large scale brain-inspired electronic systems. Specifically we welcome contributions including (but not limited to) advances in the following:

1) Emerging technologies and devices for reproducing the physics and the dynamics of real synapses (i.e. synaptic emulators), ideally on timescale ranges matching the broadness of biological timescales.
2) Emerging technologies and devices for reproducing good approximations of synaptic behavior (i.e. synaptic simulators), ideally on timescales found in biology.
3) Memory structures exhibiting differing degrees of volatility (including a) fully non-volatile over long time ranges -months-, b) fully volatile and c) devices exhibiting more than one degree of volatility at the same time -e.g. featuring a volatile and a non-volatile component-).
4) Electronic architectures that support or ideally actively exploit the characteristics of inherently unreliable devices.
5) Examples of applications or entire domains of applications where such synaptic electronics could prove of great utility.

Important note: All contributions to this Research Topic must be within the scope of the section and journal to which they are submitted, as defined in their mission statements. Frontiers reserves the right to guide an out-of-scope manuscript to a more suitable section or journal at any stage of peer review.

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