Workloads such as scientific discovery, engineering modeling and simulation, data science, real-time analytics and artificial intelligence continue to grow in complexity and scale at an ever increasing rate. To address such growth, high-performance computing (HPC) architectures are undergoing a transformative evolution. Driven by the push toward improved performance and much better energy efficiency, modern HPC systems are innovating at the hardware, software and system levels, exploiting advanced parallelism, specialized/domain-specific computing, novel memory hierarchies, innovative interconnect mechanisms and advanced storage solutions to address the demands of emerging and next-generation applications. Moreover, future HPC is evolving into systems comprising a mix of traditional digital computing, specialized AI, and quantum computing subsystems. These advancements are essential for enabling breakthroughs to meet the challenging demands for HPC.

However, the progression towards performance and efficiency introduces new system-level challenges. Efficient utilization of multi-level parallel computing (from racks to nodes to chips), scalable memory systems that address bandwidth and latency bottlenecks, integration of specialized engines, and leveraging emerging silicon technologies are all pivotal for maximizing computational throughput and flexibility. As HPC systems increasingly operate in shared-server environments and multi-tenant clouds, the compartmentalization and isolation of processes—crucial for security, resource management, and performance predictability—have emerged as key research frontiers. Additional challenges include integration of specialized subsystems such as AI and Quantum computing, which requires implementing efficient resource partitioning strategies that support specialization without sacrificing throughput. Enhancing hardware-software co-design, developing programmable fabrics, and modeling system-level tradeoffs are all critical for navigating the rapidly changing landscape of HPC architectures.

This Research Topic aims to highlight novel hardware and system-level advancements that drive the frontier of high-performance computing. We seek foundational contributions and real-world evaluations that demonstrate the impact of architectural innovations on scientific discovery, AI, and engineering workloads, among others.

We welcome original research articles, reviews, perspectives, and case studies focused on advances in HPC architectures and systems. Topics of interest include, but are not limited to:
- Innovations and breakthroughs in HPC system design and deployment
- Multi-level parallelism techniques, including rack-level, node-level and accelerator-level parallelization
- Advanced memory hierarchy, high bandwidth memory (HBM), and memory-centric architectures for HPC
- Near/in-memory processing, in-network processing
- Software frameworks and use cases in high-performance environments
- Efficient process compartmentalization, isolation, and resource partitioning for shared servers
- Hardware-software co-design for performance, efficiency, and programmability in HPC
- System modeling, benchmarking, and workload analysis for new HPC architectures
- Emerging hardware interconnects and communication fabrics
- Cloud-based HPC
- Integration with specialized subsystems: AI, Quantum
- Exploitation of emerging silicon packaging technologies for HPC, such as chiplets, 2.5D/3D integration, co-packaged optics.

Submissions that integrate theoretical innovation with practical system design, real-world deployment, or domain-specific application case studies are particularly encouraged.

Are you interested in contributing a manuscript to this Research Topic?

Advancements in HPC Architectures and Systems