With increasingly larger data volume in artificial intelligence (AI), modern processors are facing tremendous challenges in memory access (i.e., the von Neumann bottleneck), energy efficiency and latency. To meet computing and communication demand of future intelligent systems, we need fundamentally new approaches to integrate device, circuits and architecture in our hardware platform. In this context, computation immersed in memory, such as near-memory computing (NMC) and in-memory computing (IMC), is proposed to complement the conventional digital processor and improve latency and energy efficiency in AI computing by orders of magnitude. Distinguished from von Neumann architecture, NMC and IMC interleave computing and memory in a fine granularity, or even embed analog AI operations in the memory array, promising massively parallel computing with high storage density.
Leveraging new device technology and design techniques, multiple groups successfully demonstrated NMC and IMC accelerators on silicon, achieving much higher processing efficiency (e.g. TOPS/W) than their digital counterparts. The choice of memory cells ranges from SRAM and its variants, to eDRAM, Flash, and to other non-volatile memories. Despite these silicon advances, there still exist significant design challenges. Particular examples include (1) design robustness, such as lower signal-to-noise ratio (SNR) in analog computing, device- and circuit-level variations and parasitics; (2) cost in peripherals, especially the conversion between analog and digital domain; and (3) system scalability when multiple process elements (PEs) are interconnected together to complete end-to-end computing. Cross-layer solutions to address these issues will be critical to fully realize the potential of NMC and IMC, and accelerate AI computing toward the next level.
The overarching goal of this Research Topic on computation immersed in memory is to review state-of-the-art design practices, explore emerging circuit and architecture solutions, and reveal future research needs. Key topics include, but not limited to:
1. Computing methodologies and mapping to NMC and IMC;
2. Analog/digital computing with various memory technologies;
3. Integrated circuits design for NMC and IMC, as well as peripherals;
4. Heterogeneous integration in an NMC/IMC system;
5. On-chip and 2.5D/3D interconnection for large-scale design;
6. Applications of NMC and IMC in intelligent dynamic systems;
With increasingly larger data volume in artificial intelligence (AI), modern processors are facing tremendous challenges in memory access (i.e., the von Neumann bottleneck), energy efficiency and latency. To meet computing and communication demand of future intelligent systems, we need fundamentally new approaches to integrate device, circuits and architecture in our hardware platform. In this context, computation immersed in memory, such as near-memory computing (NMC) and in-memory computing (IMC), is proposed to complement the conventional digital processor and improve latency and energy efficiency in AI computing by orders of magnitude. Distinguished from von Neumann architecture, NMC and IMC interleave computing and memory in a fine granularity, or even embed analog AI operations in the memory array, promising massively parallel computing with high storage density.
Leveraging new device technology and design techniques, multiple groups successfully demonstrated NMC and IMC accelerators on silicon, achieving much higher processing efficiency (e.g. TOPS/W) than their digital counterparts. The choice of memory cells ranges from SRAM and its variants, to eDRAM, Flash, and to other non-volatile memories. Despite these silicon advances, there still exist significant design challenges. Particular examples include (1) design robustness, such as lower signal-to-noise ratio (SNR) in analog computing, device- and circuit-level variations and parasitics; (2) cost in peripherals, especially the conversion between analog and digital domain; and (3) system scalability when multiple process elements (PEs) are interconnected together to complete end-to-end computing. Cross-layer solutions to address these issues will be critical to fully realize the potential of NMC and IMC, and accelerate AI computing toward the next level.
The overarching goal of this Research Topic on computation immersed in memory is to review state-of-the-art design practices, explore emerging circuit and architecture solutions, and reveal future research needs. Key topics include, but not limited to:
1. Computing methodologies and mapping to NMC and IMC;
2. Analog/digital computing with various memory technologies;
3. Integrated circuits design for NMC and IMC, as well as peripherals;
4. Heterogeneous integration in an NMC/IMC system;
5. On-chip and 2.5D/3D interconnection for large-scale design;
6. Applications of NMC and IMC in intelligent dynamic systems;
