Guidelines

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Start your submission and get more impact for your research by publishing with us.

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Author guidelines

Ready to publish? Check out our author guidelines for everything you need to know about submission, from choosing a journal and section to preparing your manuscript.

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Editor guidelines

Reviewing a manuscript? See our editorial guidelines for everything you need to know about Frontiers’ peer review process.

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Peer review

Our efficient and rigorous peer review means you’ll get a decision on your manuscript in just 77 days.

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Publishing fees

Article processing charges (APCs) apply to articles that are accepted for publication by our external editors, following rigorous peer review.

Editors

See all (175)

yu cao

University of Minnesota

Minneapolis, United States

Specialty Chief Editor

Integrated Circuits and VLSI
subhasish mitra

Stanford University

Stanford, United States

Specialty Chief Editor

Integrated Circuits and VLSI
josé l. abellán

University of Murcia

Murcia, Spain

Associate Editor

Integrated Circuits and VLSI
hussam amrouch

University of Stuttgart

Stuttgart, Germany

Associate Editor

Integrated Circuits and VLSI

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Integrated Circuits and VLSI

Guidelines

Submit your research

Author guidelines

Editor guidelines

Peer review

Publishing fees

Editors

yu cao

subhasish mitra

josé l. abellán

hussam amrouch

Articles

Straightforward data transfer in a blockwise dataflow for an analog RRAM-based CIM system

CoFHE: Software and hardware Co-design for FHE-based machine learning as a service

XMA2: A crossbar-aware multi-task adaption framework via 2-tier masks

Energy-efficient neural network design using memristive MAC unit

Research Topics

Recent Advances on Field-Programmable Logic and Applications

Emerging Materials, Novel Circuit and System for Neuromorphic and AI Acceleration in the Big Data Era

New trends in Memristor Analysis, Modelling, and Fabrication: Applications in Circuits and Systems Design

Agile Hardware-Software Co-Design for Computing-in-Memory Accelerator - From Hardware Design to Network Optimization Perspectives