REVIEW article

Front. Electron.

Sec. Integrated Circuits and VLSI

Volume 6 - 2025 | doi: 10.3389/felec.2025.1469802

This article is part of the Research TopicExploring the Boundaries of Full-Stack AI AccelerationView all articles

Quantized Convolutional Neural Networks: A Hardware Perspective

Provisionally accepted
Li  ZhangLi Zhang1Olga  KrestinskayaOlga Krestinskaya1Mohammed  FoudaMohammed Fouda2Ahmed  Mohamed EltawilAhmed Mohamed Eltawil1Khaled  Nabil SalamaKhaled Nabil Salama1*
  • 1King Abdullah University of Science and Technology, Thuwal, Saudi Arabia
  • 2Rain Neuromorphics, San Francisco, United States

The final, formatted version of the article will be published soon.

With the rapid development of machine learning, Deep Neural Network (DNN) exhibits superior performance in solving complex problems like computer vision and natural language processing compared with classic machine learning techniques. On the other hand, the rise of the Internet of Things (IoT) and edge computing set a demand on executing those complex tasks on corresponding devices. As the name suggested, deep neural networks are sophisticated models with complex structures and millions of parameters, which overwhelm the capacity of IoT and edge devices. To facilitate the deployment, quantization, as one of the most promising methods, is proposed to alleviate the challenge in terms of memory usage and computation complexity by quantizing both the parameters and data flow in the DNN model into formats with shorter bit-width.Consistently, dedicated hardware accelerators are developed to further boost the execution efficiency of DNN models.In this work, we focus on Convolutional Neural Network (CNN) as an example of DNNs and conduct a comprehensive survey on various quantization and quantized training methods. We also discuss various hardware accelerator designs for quantized CNN (QCNN). Based on the review of both algorithm and hardware design, we provide general software-hardware co-design considerations. Based on the analysis, we discuss open challenges and future research directions for both algorithms and corresponding hardware designs of quantized neural networks (QNNs).

Keywords: Convolutional Neural Networks, quantization, hardware, In memory computing (IMC), FPGA

Received: 24 Jul 2024; Accepted: 03 Jun 2025.

Copyright: © 2025 Zhang, Krestinskaya, Fouda, Eltawil and Salama. This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) or licensor are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.

* Correspondence: Khaled Nabil Salama, King Abdullah University of Science and Technology, Thuwal, Saudi Arabia

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