Your new experience awaits. Try the new design now and help us make it even better

ORIGINAL RESEARCH article

Front. Electron.

Sec. Nano- and Microelectronics

Volume 6 - 2025 | doi: 10.3389/felec.2025.1648721

This article is part of the Research TopicSemiconductor Technologies - Materials to ChipsView all articles

Analytical Prediction of Thermomechanical Shear Strain in Solder Joints with FEA Validation in Electronic Packaging

Provisionally accepted
  • Lamar University, Beaumont, United States

The final, formatted version of the article will be published soon.

This paper presents a closed-form analytical model for predicting shear strain in chip-on-board assemblies with an array of solder balls. While the classical analytical formula estimates shear strain based on a configuration with a single solder joint at each end of the chip, it fails to account for the distributed nature of real assemblies. By applying compatibility conditions along the chip/solder ball and PCB/solder ball interfaces, and employing beam theory, the proposed model incorporates key geometric and material parameters, including chip and PCB dimensions, solder ball diameter, height, pitch, and elastic moduli, enabling accurate prediction of mechanical response under thermal loading. Results show that the classical model overestimates shear strain by more than 50 times compared to finite element analysis (FEA), whereas the proposed method yields results consistent with FEA. Hence, the proposed analytical solution presented in the paper demonstrates a significant improvement over the classical formula in prediction of shear strain.The new model reveals that in a fully populated array layout, the maximum shear strain at the outermost solder joint remains nearly constant with increasing chip size. The analysis also indicates that inner solder joints contribute minimally to mechanical support, suggesting that depopulated array designs may not compromise reliability. Additional parametric studies demonstrate that reducing the thickness or stiffness of the chip or PCB decreases overall strain levels. These findings are validated by finite element simulations. The paper concludes with a discussion of future work to address normal strain effects and inelastic behaviors in solder joints.

Keywords: shear strain, Electronic packaging, Solder joint array, Reliability, Chip on board package

Received: 17 Jun 2025; Accepted: 29 Aug 2025.

Copyright: © 2025 Bhetuwal, Zhou and Fan. This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) or licensor are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.

* Correspondence: Xuejun Fan, Lamar University, Beaumont, United States

Disclaimer: All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors and the reviewers. Any product that may be evaluated in this article or claim that may be made by its manufacturer is not guaranteed or endorsed by the publisher.