Single Event Upset Simulation and Detection in Configuration Memory

Hezekiah Austin^1,2*Chris Major^1,2Colter Barney¹Justin Williams¹Zachary Becker¹Mackenzie Smith¹Brock Lameres^1,2

• ¹Montana State University, Bozeman, United States
• ²Resilient Computing, Bozeman, United States

Single event upsets (SEU) from radiation strikes in configuration memory are potentially catastrophe due to their widespread effects. For field programmable gate arrays (FPGAs), faults in configuration memory propagate into the implemented logic design on the hardware interconnection level with unpredictable results. Two payloads consisting of a pair of quad modular redundant (QMR) FPGA-based processor were deployed to the International Space Station for 13 months. During operation, these payloads experienced a number of faults from radiation including one payload experiencing a rare multi-core fault. Investigation suggested the multi-core fault was the result of a SEE directly in a voter on the logic design or an SEE in the FPGA configuration memory changing the implemented logic. An injection procedure for the FPGA's configuration memory was developed to simulate radiation strikes in configuration memory and test fault detection. The injection procedure was paired with the QMR processor. This provided a full configuration memory testing environment where the implemented logic design was capable of detecting faults propagating from the FPGA's configuration memory. Injection throughout the configuration memory was used to create a map of particularly vulnerable locations in configuration memory and implemented logic design. Testing with injected faults produced similar results to the multi-core fault observed in orbit on the payload. The testing procedure provides a comprehensive testing strategy which pairs systematic injection in the configuration memory with a logic design capable of detecting the induced errors to localize the propagating fault in the design.