SPIKA: An Energy-Efficient Time-Domain Hybrid CMOS-RRAM Compute-in-Memory Macro

Khaled Humood^1,2*Yihan Pan²Mohammed Mughal²Grahame Reynolds²Shiwei Wang²Alex Serb²Themis Prodromakis²

• ¹University of Edinburgh, Edinburgh, United Kingdom
• ²The Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, University of Edinburgh, Edinburgh, United Kingdom

The increasing significance of machine learning (ML) has led to the development of circuit architectures suited to handling its multiply-accumulate-heavy computational load such as Compute-In-Memory (CIM). A big class of such architectures uses resistive RAM (RRAM) devices, typically in the role of neural weights, to save power and area. In this work, we present SPIKA, an RRAM-based ML workload accelerator that exploits natural signal domain conversions in order to achieve high power and throughput efficiency. Specifically, digital input signals are converted to pulse-width modulated (time-domain), then applied on the RRAM weights that convert them to analog currents, and then aggregated into digital values using a simple switch capacitor read-out system. At no point do we use high-resolution and power-hungry data converters. The design is implemented in a commercially available 180nm technology on a crossbar of size 64×128 and uses 4-bit inputs, ternary weights, and 5-bit outputs. Post-layout analysis indicates a remarkable performance of the proposed system compared to state-of-the-art with a peak throughput of 1092 GOPS and energy efficiency of 195 TOPS/W.