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CORRECTION article

Front. High Perform. Comput., 08 January 2026

Sec. Architecture and Systems

Volume 3 - 2025 | https://doi.org/10.3389/fhpcp.2025.1763887

This article is part of the Research TopicEmerging Trends in Software Tools for Exascale Application DevelopmentView all 4 articles

Correction: Processor simulation as a tool for performance engineering

This article is a correction to:

  1. Processor simulation as a tool for performance engineering

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A Correction on
Processor simulation as a tool for performance engineering

by Falquez, C., Long, S., Ho, N., Suarez, E., and Pleiter, D. (2025). Front. High Perform. Comput. 3:1669101. doi: 10.3389/fhpcp.2025.1669101

Author Estela Suarez was erroneously assigned to affiliation “SiPEARL, Maisons-Laffitte, France”. This affiliation has now been removed for author Estela Suarez.

The conflict of interest statement has been corrected to: The author(s) declared that this work was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

The original version of this article has been updated.

Keywords: high-performance computing (HPC), processor architectures, instruction set extensions, vector instructions, Arm's Scalable Vector Extension (SVE), RISC-V's RVV, performance counters, performance profiles

Citation: Frontiers Production Office (2026) Correction: Processor simulation as a tool for performance engineering. Front. High Perform. Comput. 3:1763887. doi: 10.3389/fhpcp.2025.1763887

Received: 09 December 2025; Accepted: 09 December 2025;
Published: 08 January 2026.

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Frontiers Editorial Office, Frontiers Media SA, Switzerland

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