Author Estela Suarez was erroneously assigned to affiliation “SiPEARL, Maisons-Laffitte, France”. This affiliation has now been removed for author Estela Suarez.
The conflict of interest statement has been corrected to: The author(s) declared that this work was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.
The original version of this article has been updated.
Summary
Keywords
high-performance computing (HPC), processor architectures, instruction set extensions, vector instructions, Arm's Scalable Vector Extension (SVE), RISC-V's RVV, performance counters, performance profiles
Citation
Frontiers Production Office (2026) Correction: Processor simulation as a tool for performance engineering. Front. High Perform. Comput. 3:1763887. doi: 10.3389/fhpcp.2025.1763887
Received
09 December 2025
Accepted
09 December 2025
Published
08 January 2026
Approved by
Frontiers Editorial Office, Frontiers Media SA, Switzerland
Volume
3 - 2025
Updates
Copyright
© 2026 Frontiers Production Office.
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