- Centre for Electronics Frontiers, Institute for Integrated Micro Nano Systems, School of Engineering, University of Edinburgh, Edinburgh, United Kingdom
Due to their high density, scalability, and low-power properties, 1-transistor-1-resistor (1T1R) RRAM-based crossbars have been exploited in the past. However, the series resistance of the transistor is a major problem in 1T1R crossbar arrays. This limits the maximum current available for inducing resistive switching and degrades the array’s performance. To mitigate this issue, we propose a new configuration—1-transistor-1-diode-1-resistor (1T1D1R)—in which diodes are used (including bulk source/drain parasitic diodes of the access transistor) to bypass the gating transistor during the programming operation (“write”). The proposed solution trades increased overhead in the layout area for a dramatic increase in the maximum achievable current drive on RRAM devices, resulting in the ability to deliver 1.5 mA+ with a voltage supply as low as 1.2 V using minimum-size devices (in our implementation). We designed a 32 × 32 crossbar array with on-chip peripheral circuitry in commercially available 0.18 μm triple-well CMOS technology for the proof of concept. We demonstrate bidirectional programming, showing a memristance change of ≈500 Ω for 120 and 80 pulses in positive and negative directions, respectively.
1 Introduction
With the evolution of data-intensive applications, from machine learning (ML) to deep learning (DL) (LeCun et al., 2015), processing and storing large amounts of data are the biggest challenges for the Von Neumann architecture. The Von Neumann bottleneck arises due to the long access time per operation in fetching both instructions and data from memory via a single bus. It thus limits the overall performance of a system, dissipating a large amount of energy. To solve this technological bottleneck, the emergence of non-volatile memory (NVM) became a new paradigm, with technologies that offer promising features over classical memory technologies, such as high density, low leakage power, scalability, and computing-in-memory (CIM) capabilities (Staudigl et al., 2022). There are numerous NVM technologies, including resistive random-access memory (RRAM), phase change memory (PCM), spin-transfer-torque magnetic RAM (STT-MRAM), and ferroelectric field effect transistors (FeFETs). Some have even become commercially available, such as TSMC’s 40 nm RRAM (Chou et al., 2018) and Intel’s 22 nm RRAM (Jain et al., 2019), TSMC’s 40 nm PCM (Wu et al., 2018), Intel’s 22 nm STT-MRAM (Wei et al., 2019), and Samsung’s 28 nm STT-MRAM (Song et al., 2018), while doped
Numerous studies have been conducted on the design of memory cells without using NVM technologies. Kim (2008) designed a single-bit memory cell using bipolar transistors, external Schottky diodes, and a capacitor. It was characterized by a lower word line loading, as it bypasses the transistors during programming. Prabhat and Myers (2020) demonstrate the use of the body bias technique to accommodate SRAM cells to operate at a lower operating voltage. Other SRAM-based designs also exist that use body bias technology to increase power efficiency (Mishra et al., 2021; Faraji et al., 2014). Houghton et al. (1998) designed a gain cell in a memory array using two transistors, one diode, and one capacitor. The main focus of their design is the gain cells used for the read-out operation and the diodes that prevent the conduction of the read transistor in the opposite direction.
RRAM/Memristor is considered a game-changing electronic device that can store multi-bit information at extremely low operational power (Stathopoulos et al., 2017; Chen et al., 2020). Moreover, due to its scalability, fast switching speed, and excellent cmos compatibility, it is considered competitive in next-generation memory devices (Berdan et al., 2014; Guan et al., 2012; Yu et al., 2012). RRAM-based crossbar arrays have been widely studied for in-memory computing and neuromorphic applications for their benefits in speeding computation and high area efficiency (Majhi et al., 2017; Lee et al., 2007). However, “raw” arrays suffer from “sneak current”, also known as “sneak path current,” whereby undesirable current flows through unselected or non-intended memory cells. This is demonstrated in Figure 1, where the green dotted path is the selected cell, while the red path results from unselected cells. Thus, the power which inherently compromises measurement accuracy in resistance states is drained, possibly even causing unintended writing on unselected cells. Multiple solutions exist, both at the biasing scheme and device levels. Biasing schemes (Chen, 2013; Deng et al., 2013; Li et al., 2021), effective at large write and read voltages, constrain leakage by applying some intermediate voltages to all the unselected cells within the array, thus preventing undesired disturbance to the stored data. Very recently, Chen et al. (2024) demonstrated that enhancing self-rectifying behavior in memristive cells offers better performance by characterizing the sneak path current in passive crossbar arrays. However, the dominant solution currently for circuit designers is using a selector— also known as an “access device”—connected in the path of the RRAM device, giving rise to the 1-selector-1-RRAM (1S1R) configuration. The selector may be a diode (1-diode-1-RRAM; 1D1R), a transistor (1-transistor-1-RRAM; 1T1R), or a mixed-ionic–electronic–conduction (MIEC) selector (Li et al., 2021; Huang et al., 2011; Burr et al., 2012; Chen et al., 2023). Transistor selectors are popular because they are directly implementable in cmos and have extra control flexibility via gate signaling. However, transistor selectors also bottleneck the high scalability of RRAM into high-density crossbar arrays and introduce significant series resistance, requiring compensation in the form of higher write voltages applied across the 1T1R stack. Dinh et al. (2016) used one transistor, one diode, and one RRAM to design a memory device. Here, the access transistor was switched on during programming and reading, while the parasitic diode was used during the erase mode. While this approach is interesting, the transistors’ series resistance is a major bottleneck. Additionally, this approach cannot be used for bi-directional programming and multi-bit read–write at low voltages. Alshaya et al. (2023) and Fouda et al. (2018) found that the switching time for the 1T1R configuration is high and increases as the crossbar size increases.

Figure 1. RRAM-based
To circumvent this, a new cell structure—1-transistor-1-diode-1-resistor (1T1D1R) uses metal oxide-semiconductor (MOS) diodes, including the bulk-S
We have thus far successfully validated the 1T1D1R cell in the 0.18
2 1T1D1R memory cell design and operations
We propose a 1T1D1R structure, a tileable “memory cell” that when placed in an array configuration, can perform three basic operations: a) bidirectional (a.k.a. bipolar) programming/write; b) read; c) low-power idle mode (park). The 1T1D1R cell shown in Figure 2 has six terminals. Two of these arise as the nmos transistor sits on an insulated substrate formed by a nested

Figure 2. Layout view of 1T1D1R. (a) 2-D cross-section of 1T1D1R configuration along the cut line. Red dashed line and solid green line paths with arrows illustrate negative and positive programming directions, respectively. (b) Top view showing the nmos footprint.
The two Nwells are connected via metal layers, and the terminal is named “

Figure 3. (a) 1T1D1R circuit diagram showing diodes and RRAM. (b–d) Terminal voltages for (b) “positive” programming with current direction from

Figure 4. (a) Conventional 1T1R cell. Illustrates terminal voltages for (b) positive programming with the current direction from
2.1 Circuit operations
2.1.1 Programming mode
RRAM devices store data in their resistive states. Frequently, a “1” is stored as a suitably defined low resistive state (LRS) and “0” as a high resistive state (HRS). However, to program either of these values, potentially significant current must be passed through the RRAM device or “stuck-at” faults may occur.
In programming mode, terminal
2.1.2 Read mode
For the read operation, the proposed 1T1D1R configuration maintains backward compatibility with standard 1T1R and offers multiple options. In all cases,
2.1.3 Park mode
The memristors in the memory array are used as memory storage elements and are therefore electrically reconfigurable (they can be toggled repeatedly between their low and high conductance states called OFF and ON). There are several ways to “park” this circuit (switch it off). A possible configuration is with

Figure 5. Timing diagram for programming (positive and negative), reading, and park operations.
2.2 Array design: no sneak current path
Here we examine the behavior of a

Figure 6. Programming and read paths of the target cell (2,1) in a

Table 1. Voltage levels for the operation of a (2,1) target cell in a
3 Memristor and 1T1D1R cell response
3.1 Memristor characteristics
Multiple memristor models exist in the literature (Kvatinsky et al., 2015; Messaris et al., 2017; Messaris and Serb, 2018). For this study, we use our in-house fabricated valance change memory (VCM) metal–insulator–metal structure

Figure 7. Typical I-V characteristic showing the pinched hysteresis loop of our in-house fabricated memristor model. The inset shows the test bench and the input voltage. The model’s parameters are presented in the appendix of Maheshwari et al. (2021a).
3.2 1T1D1R versus 1T1R under DC and transient response
RRAM device programming in both forward (positive) and reverse directions (negative) is done by setting the terminals

Figure 8. Current and voltage drive

Figure 9. 1T1D1R versus 1T1R transient response for programming and read pulse width of 1
4 32 × 32 crossbar array design and analysis
4.1 Architecture design overview
For proof-of-concept, we designed a

Figure 10. (a)
The target cell is selected based on the row (
4.1.1 32 × 32 array design
To minimize the crossbar area, 32 nmos transistors are encapsulated inside

Figure 11. Layout of a
4.1.2 Row circuitry
The row circuitry (RC) constitutes logic for

Figure 12. Implementation of 32 × 32 row circuitry, used to generate row signals SEL, NW, and PW. Input address and data are gated with a write/read enable signal.

Figure 13. Gate-level implementation showing row logic circuitry. (a) SEL logic set either to VDD or GND. (b) Pwell logic used for negative programming. (c) Nwell logic used for positive programming.

Table 2. Row logic circuitry truth table generating SEL, PW, and NW signals for positive programming, negative programming, read, and park mode.
4.1.3 Column circuitry
The column circuitry (CC) constitutes logic for

Figure 14. Column circuitry for reading either single cell or bunch of cells, either row or column-wise. (a) Out-logic for reading stored value in a cell. (b) LN logic for setting required voltage for writing and reading.

Table 3. Column logic circuitry truth table generating LN and Out signals for positive programming, negative programming, read, and park mode.
4.2 Timing analysis and evaluation
The post-layout simulated waveform for the

Figure 15. Post-layout simulated results for 32 × 32 cells with peripheral circuits. Write and read pulse widths are 1
The final comparison of 1T1D1R with 1T1R cell is shown in Table 4. Due to the two wells, the cell has a higher area; however, there is a negligible change in the programming energy consumption. The proposed design shows an increased current drive, recorded at 1 k

Table 4. Comparison of 1T1R and proposed 1T1D1R single cell and post layout result of
5 Discussion and conclusion
We obtained a
Data availability statement
The original contributions presented in the study are included in the article/supplementary material; further inquiries can be directed to the corresponding author.
Author contributions
SM: Conceptualization, Formal Analysis, Investigation, Methodology, Validation, Writing – original draft, writing – review and editing. AS: Conceptualization, Project Administration, Supervision, Visualization, Writing – review and editing. TP: Conceptualization, Funding acquisition, Supervision, Writing – review and editing.
Funding
The author(s) declare that financial support was received for the research and/or publication of this article. This work was supported by the Engineering and Physical Sciences Research Council (EPSRC) Research Grant EP/R024642/1-2 (codename FORTE) and the Royal Academy of Engineering Chair in Emerging Technologies under Grant CiET1819/2/93.
Conflict of interest
The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.
Generative AI statement
The author(s) declare that no Generative AI was used in the creation of this manuscript.
Publisher’s note
All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors and the reviewers. Any product that may be evaluated in this article, or claim that may be made by its manufacturer, is not guaranteed or endorsed by the publisher.
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Keywords: crossbar array, low voltage, RRAM, 1T1R, parasitic diode, programming, selector technologies
Citation: Maheshwari S, Serb A and Prodromakis T (2025) Low-voltage programming of RRAM-based crossbar arrays using MOS parasitic diodes. Front. Nanotechnol. 7:1587700. doi: 10.3389/fnano.2025.1587700
Received: 04 March 2025; Accepted: 02 May 2025;
Published: 03 July 2025.
Edited by:
Syed Arshad Hussain, Tripura University, IndiaReviewed by:
Ziang Chen, Friedrich Schiller University Jena, GermanySherin Thomas, Indian Institute of Technology Ropar, India
Sarappadi Narasimha Prasad, Manipal Institute of Technology Bengaluru, India
Copyright © 2025 Maheshwari, Serb and Prodromakis. This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) and the copyright owner(s) are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.
*Correspondence: Sachin Maheshwari, bWFoZXNod2FyaS5zYWNoaW5AZWQuYWMudWs=