Low-voltage-driven memristor framework for efficient neuromorphic computation with STDP functionality

In this work, a low-voltage-driven theoretical memristor framework is presented with its in-depth parametric evaluation and its neuromorphic computing functionalities, including spike-time dependent plasticity (STDP) via Hebbian learning rules. The presented memristor model efficiently emulates the fundamental pinched hysteresis loop under the application of an input voltage amplitude of 10 mV, which enables its adaptability in low-voltage operation. Moreover, the memristor model efficiently emulates its response under the variations in the applied voltage, initial state variable, boundedness of state variable, control parameter for the rate of change of state variable, experimental fitting parameters, magnitude of exponentials, and conductivity slope parameters. These aforementioned parameters significantly affect the response of the memristor model, which further requires their optimization to understand their impact on the memristor characteristics. Therefore, these parameters are scrutinized based on their strong to weak impact on the memristor model response and its suitability in the neuromorphic computation. Additionally, the presented memristor model efficiently emulates various neuromorphic computing characteristics, including potentiation, depression, conductance tuneability, short-term memory (STM), long-term memory (LTM), transition from STM-to-LTM and vice versa, paired pulse facilitation (PPF), synaptic re-stimulation process, and STDP via Hebbian learning rules. Therefore, the presented theoretical memristor framework can be further useful in the in-memory computation circuit hardware, low-voltage logic operation, pattern recognition, and neuromorphic computing.

Introduction

In the current era of low-voltage data processing and neuromorphic computation hardware, memristor plays a very important role due to its several unique properties, including non-volatile nature (Feali, 2021), fast switching speed (Torrezan et al., 2011), remarkable device scaling potential (Kim et al., 2021), and complementary metal oxide semiconductor (CMOS) compatibility (He et al., 2021). Generally, a memristor is a two-terminal device in which high-k materials are sandwiched between top and bottom electrodes (Dahiya et al., 2025), and under the application of external potential, it is switched between two distinct resistance states, i.e., low resistance state (LRS) and high resistance state (HRS) (Basnet et al., 2023). The first experimental and its corresponding theoretical framework was proposed by S. Williams et al (Strukov et al., 2008) in 2008, in which TiO₂ was sandwiched between two Pt electrodes. The experimental outcome of this Pt/TiO₂/Pt memristor was further analytically modeled through mathematical formulation (Strukov et al., 2008). Later, various theoretical models have been reported, including the non-linear ion drift model (Yang et al., 2008), Simmons tunnel barrier model (Pickett et al., 2009), Yakopcic model (Yakopcic et al., 2011), and Threshold adaptive memristor model (Kvatinsky et al., 2013), which certainly emulated the fundamental properties of the memristor.

Additionally, in the non-linear ion drift model, applied voltage produces a strong electric field in the thin film structure, leading to the nonlinear ionic transport and lowering of the energy barrier. However, in the nonlinear dopant drift model, the state cannot be fully reversed, and therefore, a typical window function was required (Yang et al., 2008). In the Simmons tunnel barrier model (Pickett et al., 2009), a series resistance was introduced with an electron tunneling barrier, which captured the nonlinear and asymmetric switching. Next, the Yakopcic model (Yakopcic et al., 2011) described the memristive behavior using a threshold-based nonlinear state equation coupled with a voltage-controlled current equation. However, further study revealed that the Yakopcic model (Yakopcic et al., 2011) has certain discrepancies, including a less nonlinear profile at the device boundaries and a higher current amplitude as reported by Kumar et al. (2020). To mitigate the discrepancies of the Yakopcic model, Kumar et al. (2020) have proposed a threshold-independent analytical model that significantly improved the device characteristics by 16.66%, and enhanced the nonlinear behavior of drift current at the device boundaries through the use of a modified window function, imposing additional boundary conditions, and a novel state variable. Furthermore, Gautam et al. (2022) and Kumar et al. (2021) also demonstrated analytical memristor frameworks that effectively emulated the various memristive characteristics, including resistive switching responses, synaptic tuneability, potentiation, depression, and synaptic re-stimulation. Moreover, these reported memristor frameworks (Gautam et al., 2022; Kumar et al., 2021) were also verified through experimental data of Y₂O₃-based memristive devices as reported by Das et al. (2018).

However, all these aforementioned memristor frameworks successfully emulated resistive switching responses (Strukov et al., 2008; Yang et al., 2008; Pickett et al., 2009; Yakopcic et al., 2011; Kvatinsky et al., 2013; Kumar et al., 2020; Gautam et al., 2022; Kumar et al., 2021), synaptic tuneability (Kumar et al., 2021), potentiation and depression properties (Kumar et al., 2020; Gautam et al., 2022; Kumar et al., 2021), and synaptic re-stimulation process (Gautam et al., 2022), but all these models required significantly higher input voltage. Additionally, all these models have not demonstrated detailed parametric evaluation, and crucial neuromorphic computing characteristics, including short-term memory (STM), long-term memory (LTM), transition from STM-to-LTM and vice versa, paired pulse facilitation (PPF), and spike time dependent plasticity (STDP) via Hebbian learning rules. Moreover, to the best of the authors’ knowledge, there is no systematic and detailed theoretical memristor framework study reported to date that covers these parametric evaluations and neuromorphic computing characteristics together. Therefore, the presented work effectively fulfils the literature gap and demonstrates in-depth neuromorphic computing through a theoretical memristor framework.

In this work, a comprehensive parametric evaluation and in-depth investigation of neuromorphic computing functionalities through a memristor model are discussed. The proposed memristor model is experimentally validated by utilizing experimental data of the Y₂O₃-based memristor (Das et al., 2018), as reported in our previous work (Kumar et al., 2020). Based on these validated results, we have extended this memristor framework (Kumar et al., 2020) in the present work to perform an in-depth parametric evaluation, ranging from fundamental memristive switching behaviour to its neuromorphic computing capabilities. Herein, a detailed parametric variations study has been implemented, which covers a wide range of parameter values and their impact on the switching responses of the memristor. Additionally, this work also explores the extended neuromorphic computing functionalities, including paired-pulse facilitation (PPF), STM, LTM, and transition from STM-to-LTM and vice versa, STDP via Hebbian learning rules, and re-stimulation processes. Therefore, the presented theoretical memristor framework can be useful to perform in-memory computation, low-voltage-driven logic operations, and neuromorphic computation.

Theoretical memristor framework

In this section, a detailed theoretical memristor framework is discussed, which defines its mathematical expressions including current-voltage (I-V) relationship (Kumar et al., 2020), threshold voltage independent state variable (x(t)), programming voltage (G (V(t)), and window functions (W_p and W_n) with appropriate boundary conditions. Equation 1 describes the I-V relationship of the memristor framework.

$I\left(t\right)=\left\{\begin{array}{c}{a}_{1}x\left(t\right)\mathit{sin}h\left(b_{1}V\left(t\right)\right),V\left(t\right)\ge 0\\ a_{2}x\left(t\right)\mathit{sin}h\left(b_{2}V\left(t\right)\right),V\left(t\right)<0\end{array}\right\}(1)$

where, a₁ and a₂ are experimental fitting parameters, b₁ and b₂ are the conductivity slope controlling parameters for the positive and negative applied input voltage, respectively. The utilized memristor model uses a separate conductivity control parameter for both voltage polarities, as stated in Equation 1, that offers better control over the device hysteresis loop.

In general, memristive devices exhibit higher conductivity under positive voltage bias (if the SET process is associated with positive voltage) as compared to that under negative bias (Das et al., 2018; Chang et al., 2011a). Here, in this memristor framework, the SET process is also associated with the positive voltage polarity, and the movement/migration of ions/vacancies takes place in the switching layer, which overall changes the resistance of the memristive system (Das et al., 2018). Additionally, this memristor framework is independent of threshold voltage, and the variation in state variable (x(t)) is described by Equation 2, in which it depends on various parameters, including G (V(t)), α_p, α_n, W_p, W_n, x, and U(t).

$\frac{dx}{dt}=\left\{\begin{array}{c}G\left(V\left(t\right)\right)e^{-{\alpha }_{\mathrm{p}}U\left(x-x_{\mathrm{p}}\right)\left(x-x_{\mathrm{p}}\right)}\left(1+\left(W_{\mathrm{p}}-1\right)U\left(x-x_{\mathrm{p}}\right)\right),V\left(t\right)>0\\ G\left(V\left(t\right)\right)e^{{\alpha }_{\mathrm{n}}U\left(x_{\mathrm{p}}-x\right)\left(x-x_{\mathrm{p}}\right)}\left(1+\left(W_{\mathrm{n}}-1\right)U\left(x_{\mathrm{p}}-x\right)\right),V\left(t\right)<0\end{array}\right\}(2)$

where, G (V(t)) is the programming voltage, and it depends on several parameters such as the magnitude of exponentials (A_p and A_n) and applied input voltage V(t), which is described by Equation 3. U(t) defines the unit step function.

$G\left(V\left(t\right)\right)=\left\{\begin{array}{c}{A}_{\mathrm{p}}\left(e^{V\left(t\right)}-1\right),V\left(t\right)>0\\ -A_{\mathrm{n}}\left(e^{-V\left(t\right)}-1\right),V\left(t\right)<0\end{array}\right\}(3)$

where, W_p and W_n are the window functions, and these window functions bound the device state variable between 0 and 1. In this memristor framework, an additional boundary condition has been imposed on the window function, i.e., x_p + x_n = 1. Here, Equations 4, 5 describe the window functions.

$W_{\mathrm{p}}=\frac{x_{\mathrm{p}}-x}{x_{\mathrm{n}}}+1(4)$

$W_{\mathrm{n}}=\frac{x}{x_{\mathrm{p}}}(5)$

As described in Equations 4, 5, W_p controls the boundary of the state variable when x(t) approaches 1, and W_n controls the boundary of the state variable when x(t) approaches 0. The physical interpretation and range of the variations of these parameters are tabulated in Table 1.

Table 1

Table 1. Physical interpretation and range of parameters for the memristor framework to emulate switching responses.

Results and discussion

To investigate the impact of various parameters on the resistive switching response of the memristor framework, all aforementioned parameters, as described in Table 1, are varied and optimized within a certain range. At the initial stage, the resistive switching characteristics of the memristor are simulated by applying the sinusoidal waveform with different peak-to-peak voltages ranging from 10 mV to 5.5 V. Figures 1a–f shows the resistive switching responses over the input voltage range from 10 mV to 900 mV, which shows the low-voltage driven ability of the memristor framework. The obtained pinched hysteresis loop in the switching responses is well aligned with the fundamental fingerprint of the memristor (Chua, 2014), which further signifies that the memristor framework can successfully simulate the memristor characteristics.

Figure 1

Figure 1. Resistive switching responses at different applied voltages: (a) 10–20 mV, (b) magnified 10 mV, (c) 50–60 mV, (d) 90–100 mV, (e) 400–500 mV, and (f) 800–900 mV. At 10 mV, the memristor framework exhibits a very narrow pinched hysteresis loop as shown in Fig. (b).

Herein, it can also be noted that under the varied amplitude of input voltage, the overall memristor currents are also increased (300 nA at 10 mV and 5 mA at 5.5 V). Additionally, the pinched hysteresis loop area is also expanding with the increment in the voltage amplitude, which is described by the fact that increasing the electric field has a strong impact on the movement of ions/vacancies within the switching layer. Figures 2a–e exhibits the switching responses of the memristor framework under the application of 1 V–5.5 V. Moreover, at the input voltage amplitude beyond 2 V, the switching responses of the memristor framework seem to resemble ‘diode behavior’, and further increment in the voltage amplitude deteriorates the area of the pinched hysteresis loop, which significantly affects the memory capability of the memristor. The disruption in the hysteresis loop area under high input voltage can be associated with the uncontrolled and fast ionic/vacancies motion within the switching layer (Gautam et al., 2022; Sun et al., 2019; Nikam et al., 2021; Lee et al., 2021). The obtained switching outcomes revealed that the memristor framework can efficiently emulate the fundamental memristor characteristics over a wide range of input voltage amplitudes.

Figure 2

Figure 2. Resistive switching responses at different applied voltages: (a) 1–1.5 V, (b) 2–2.5 V, (c) 3–3.5 V, (d) 4–4.5 V, (e) 5–5.5 V.

The frequency-dependent resistive switching characteristics are also simulated with the range of 1–50 kHz, as shown in Figures 3a,b. As observed, the pinched hysteresis loop becomes narrower when the frequency increases. This is another signature of memristor behaviour, which explains that at the above critical frequency, the hysteresis loop area decreases as the frequency of applied voltage increases (Adhikari et al., 2013). In addition, the state variable is inversely proportional to the excitation frequency (Dongale et al., 2015). Consequently, the memristor state variable has enough time to settle at a lower frequency, leading to a non-linear resistor-like behavior. In contrast, at higher frequencies, the input signal changes too rapidly for the state variable to adjust, leading to a reduced hysteresis loop area, resembling the linear resistor characteristics (Chua and Kang, 1976). The obtained results are in good agreement with the previously reported literature (Dongale et al., 2015; Pershin and Ventra, 2011; Dongale et al., 2014).

Figure 3

Figure 3. Frequency-dependent switching characteristic ranging from (a) 1 kHz–50 kHz, (b) 30 kHz–50 kHz. Switching responses at different X_int value ranging from 0.1 to 1 at different applied voltage: (c) 0.2 V, (d) 0.5 V, (e) 1 V. Switching characteristics at different A_p: (f) 0.1 to 1.0, (g) 1.1 to 2.0, (h) 2.1 to 3.0, and (i) Switching characteristics at different A_n value varying from 0.1 to 2.0 at the value of A_p is 0.1.

The impact of the initial state variable (bounded between 0.1 and 1) is simulated at the different applied voltages of 0.2, 0.5, and 1 V as shown in Figures 3c–e. Herein, 0.1 and 1 initial states dictate that the device is in the HRS and LRS state, respectively. The obtained outcomes suggested that the switching responses are strongly dependent on the initial state variable. Initially, the device exhibits a high resistance state because the ions/vacancies spread along the volume of the switching layer, which hinders the current flow from the top to bottom electrodes (Chiu, 2014). In contrast, as the initial state variable approached 1, the device attained the LRS, depicting the formation of a conductive path between the electrodes, keeping the device current positive (Zhu et al., 2022). Furthermore, varying the initial state variable X_int unveils the filamentary resistive switching as X_int = 0.1 corresponds to rupture of filament or HRS, and X_int = 1 corresponds to formation of filament or LRS.” Furthermore, at X_int = 1, the observed I-V behaviour is almost linear, which indicates that the internal state has reached its upper boundary. Mathematically, in the positive bias, the window function collapses to zero as the state approaches X_int = 1, and the state-evolution term, $\frac{dx}{dt}$ is suppressed by the window function. Such a type of behaviour is a fundamental property of nonlinear-drift memristor models, which was described in the various models (Pickett et al., 2009; Yakopcic et al., 2011). After saturation, no further modulation of the device conductance/resistance occurs, and the memristor behaves as a resistor, resulting in a quasi-linear I-V response. On the other hand, under negative bias, the backward drift term and the corresponding window function remain non-zero at X_int = 1. The negative sweep, therefore, pulls the state away from the saturated boundary, restarting the internal dynamics, and a hysteresis loop is observed. Similar trends are observed for applied voltages of 0.5 V and 1 V. However, two orders of higher current are observed for an applied voltage of 1 V, indicating more stable and robust filament formation under higher electric fields in comparison to 0.2 V and 0.5 V.

Next, A_p and A_n are known as the magnitude of the exponential term, which demonstrates the rate of change of the state variable under the positive and negative biases, respectively, as shown in Figures 3f–i. These parameters regulate the speed of ions/vacancies motion, which can be associated with the dielectric materials used as the switching layer (Yakopcic, 2014). The obtained result revealed that the increase in the A_p has a significant improvement in the current under the positive biasing, which is attributed to the faster migration of ions/vacancies leading to the formation of the conductive filament. However, during the negative biasing, the hysteresis loop shrinks, which might be due to the slower ion/vacancy movement compared to the positive biasing. Furthermore, under negative bias, the parameter A_n plays a pivotal role in controlling the device characteristics. The increase in A_n leads to a wider hysteresis loop, depicting a stronger nonlinear response in the switching characteristics, which further suggests that higher A_n values promote more pronounced ion/vacancies movement during the reset process (Kumar et al., 2020).

On the other hand, x_p and x_n denote the points at which the state variable begins to experience nonlinear damping, while a_p and a_n are the corresponding control parameters for the damping under positive and negative bias, respectively. The increase in x_p and x_n leads to more noticeable nonlinear behaviour in the device under both positive and negative bias (see Figures 4a,b). Furthermore, increasing a_p enhances the rate of change of the state variable under positive bias, which is reflected in a sharp rise in current as depicted in Figures 4c–e. However, under negative bias, the state variable saturates, and thus variation in a_n has no longer an impact on the switching responses as shown in Figure 4f. These parameters can be associated with the electrode’s materials since the selected electrode materials may react to the switching layer differently (Dongale et al., 2014).

Figure 4

Figure 4. (a) Resistive switching characteristics with the variation in x_p from 0.1 to 0.9, (b) Switching response with the variation in x_n from 0.1 to 0.9. Switching characteristics with the variation in a_p: (c) 0.1 to 0.5, (d) 1.1 to 1.5, (e) 2.1 to 2.5, and (f) Switching characteristics with the variation in a_n from 5 to 30.

In the memristor framework, a₁ and a₂ are the experimental fitting parameters that are closely associated with the thickness of the switching layer. A thinner switching layer allows more electrons to tunnel through the barrier, resulting in increased conductivity. The b₁ and b₂ are parameters that control the slope of the conductivity under positive and negative applied voltages, respectively. The obtained outcomes indicate that increasing a₁ enhances the overall conductivity of the device (see Figure 5a). However, variations in a₂ do not significantly affect the switching response (see Figure 5b). Further, increasing the b₁ parameter significantly enhances the non-linear resistive switching responses and widens the hysteresis window (see Figures 5c,d. However, a higher value of b₁ can lead to saturation, suggesting the device reaches a maximum non-linearity (NL) limit, as depicted in Figure 5e. However, switching response in the hysteresis loop remains constant for all values of b₂, suggesting the device response is insensitive to b₂, as shown in Figure 5f. As investigated, both a₂ and b₂ are associated with the negative voltage polarity, in which the memristor is in the RESET state; therefore, the impact of these parameters on the switching response is not reflected. Additionally, this memristor framework efficiently emulates the different conductive states by modulating the parameter b₁. As observed, the memristor framework provides an enhanced memory window and different conductive states, as displayed in Figures 5g–k. The multiple conductive states in the memristor are already achieved by adjusting the compliance current, programming pulse time scheme, and applying different RESET voltages (Ambrogio et al., 2014; Reuben et al., 2019; Jiang et al., 2016). It is evident that the multiple conductance states can be finely tuned by modulating the value of parameter b_1, as it is associated with the conductivity control parameter under the application of positive voltage. Herein, the variation in the current from 88.4 nA to 65.4 µA is achieved by varying b₁ from 0.1 to 5, respectively, at the voltage of applied input voltage of 1 V, as shown in Figure 5l.

Figure 5

Figure 5. (a) Resistive switching characteristics with the variation of a₁ from 0.1 × 10⁻⁸ to 1.0 × 10⁻⁸, (b) Switching characteristics with the variation of a₂ from 0.1 × 10⁻⁸ to 1.0 × 10⁻⁸. Switching characteristics with the variation of b₁: (c) 0.1 to 1.0, (d) 2.1 to 3.0, (e) 4.1 to 5.0, (f) Switching response with the variation of b₂ from 0.1 to 1.0. Multilevel switching response under the modulation in the values of parameter b₁ from (g) 0.1 to 1, (h) 1.1 to 2, (i) 2.1 to 3 (j) 3.1 to 4, and (k) 4.1 to 5, and (l) multiple conducting states.

In the neuromorphic computing, conductance tuneability, potentiation, depression, post-synaptic current (PSC) response, PPF, STM, LTM, transition from STM to LTM and vice-versa, synaptic re-stimulation, and STDP are all important characteristics, and these are highly recommended to implement neuromorphic computing functionalities in a memristor framework. Herein, the memristor current (or conductance) tuneability characteristics are simulated over a total duration of 20 s using a train of 40 positive/negative pulses with amplitudes ranging from ±0.3 V to ±1.5 V. The memristor current is evaluated for three different pulse widths (PW) of 250, 100, and 10 m. Since the total simulation time is kept constant, the pulse interval was adjusted accordingly, resulting in intervals of 250, 400, and 490 m for PWs of 250, 100, and 10 m, respectively. The memristor current is a function of pulse amplitude (±0.3 V, ±0.5 V, and ±0.8 V) and PW, as shown in Figures 6a–f. As observed from Figure 6a, the current is increased from 7.70 mA to 16.12 mA, corresponding to a 109% increment for a PW of 250 m. At a PW of 100 m, the current increased from 7.80 mA to 11.30 mA (44% increment), while at 10 m, the current increased only slightly from 7.71 mA to 8.08 mA (4% increment). Similarly, the memristor current is a function of pulse amplitude (±1 V and ±1.5 V) and PW, as presented in Figures 7a–d.

Figure 6

Figure 6. Current tuneability response of the memristor framework under the pulse amplitude of: (a) 0.3 V, (b) −0.3 V, (c) 0.5 V, (d) −0.5 V, (e) 0.8 V, and (f) −0.8 V. Herein, under each voltage pulse amplitude, different PWs (250, 100, and 10 ms) have been utilized.

Figure 7

Figure 7. Current tuneability response of the memristor framework under the pulse amplitude of: (a) +1 V, (b) −1 V, (c) +1.5 V, (d) −1.5 V. Herein, under each voltage pulse amplitude, different PWs (250, 100, and 10 ms) have been utilized.

These findings can be interpreted in terms of both PW and inter-pulse interval. In the context of inter-pulse interval, a smaller change in current is observed at longer intervals, as evident from the 4% change at an inter-pulse interval of 490 m. On the other hand, a larger PW results in a higher current change, enabling the transition from short-term plasticity (STP) to long-term plasticity (LTP). The obtained outcomes are in good agreement with the previous reported literature (Tang et al., 2022). Additionally, the variation of pulse amplitude shows a significant impact on the memristor current, as evident from Figures 6a–f and Figures 7a–d. As seen, the increase in the pulse amplitude from ±0.3 V to ±1.5 V leads to a rise in the initial current from 7.76 mA to 315 mA. As a result, the memristor current can be effectively modulated by altering the pulse amplitude, PW, and inter-pulse interval, which is well recognized in several reported literature (Yan et al., 2018; Huang et al., 2023).

Moreover, the proposed memristor framework successfully emulated the synaptic learning characteristics in terms of potentiation (P) and depression (D) processes. However, current in both processes can be attributed to the different physical mechanisms governing filament formation and dissolution. During potentiation, the conductive filament is driven by positive applied voltage, which enhances ion migration, resulting in conductance (or current) increases. On the other hand, under negative voltage polarity, the rupture of filaments is typically limited by ionic back-diffusion and reduced local heating due to lower conductance (or current) levels. Herein, the observed asymmetry in the potentiation and depression current is well consistent with the previous studies (Yang et al., 2008; Hu et al., 2013; Waser et al., 2009; Ielmini, 2011).

Further, the memristor current is plotted as a function of pulse number, whereas a total of 80 pulses has been applied, and out of these 80 pulses, 40 pulses have positive amplitude, inducing potentiation, followed by 40 negative pulses, inducing depression. The current responses for a pulse amplitude of ±0.3 V with PWs of 250, 100, and 10 m are shown in Figures 8a–c. A combined plot with normalized current for different PWs is presented in Figure 8d. To calculate the NL factor in synaptic learning responses, a normalized forward and backward plot can be useful, as depicted in Figure 8e, whereas it can be observed that the degree of NL decreases as the PW is reduced to 10 m. The following mathematical expression (see Equation 6) is utilized to compute the NL factor (Kumar et al., 2025).

$NL=\mathit{Max}\left|G_{\mathrm{P}}\left(n\right)-G_{\mathrm{D}}\left(n\right)\right|forn=1toN(6)$

Figure 8

Figure 8. Synaptic learning behavior of the memristor framework under potentiation and depression mechanisms at pulse amplitude of ±0.3 V: (a) PW of 250 ms, (b) 100 ms, (c) 10 ms, (d) Combined normalized current plot at ±0.3 V with different PWs 250, 100, 10 ms, and (e) Normalized synaptic current behaviors at pulse amplitude of ±0.3 V with different PWs 250, 100, 10 ms to compute NL factor.

Here, G_P(n) and G_D(n) are associated with the conductance values after the nth P-pulse and nth D-pulse, respectively. The values of the NL factors are calculated as 0.35, 0.21, and 0.03 for the PW of 250, 100, and 10 m, respectively.

Similarly, for a pulse amplitude of ±0.5 V, the memristor current is increased from 21.77 mA to 62.75 mA, corresponding to a 188% increment for a PW of 250 m. At a PW of 100 m, the current is increased from 21.50 mA to 39.50 mA (83% increment), while at a PW of 10 m, the current is slightly increased from 21.32 mA to 23.00 mA (7% increment), as shown in Figures 9a–c. For the depression process, the current varies from −63.60 µA to −1.07 µA for 250 m, −41.30 µA to −22.41 µA for 100 m, and −23.04 µA to −21.34 µA for 10 ms PW. These results indicate that at a pulse amplitude of ±0.5 V, the current response is significantly higher compared to that observed at ±0.3 V. A combined plot of normalized current for different PWs is presented in Figures 9d,e. The values of NL factors are 0.43, 0.31, and 0.06 for the PWs of 250, 100, and 10 m, respectively.

Figure 9

Figure 9. Synaptic learning behavior of the memristor framework under potentiation and depression mechanisms at pulse amplitude of ±0.5 V: (a) PW of 250 ms, (b) 100 ms, (c) 10 ms, (d) Combined normalized current plot at ±0.5 V with different PWs 250, 100, 10 ms, and (e) Normalized synaptic current behaviors at pulse amplitude of ±0.5 V with different PWs 250, 100, 10 ms to compute NL factor.

Further, for a pulse amplitude of ±0.8 V, the memristor current is increased from 61.40 mA to 194.60 mA, corresponding to a 216% increment for a PW of 250 m. At a PW of 100 m, the current is increased from 61.90 mA to 154.28 mA (149% increment), while at a PW of 10 m, the current is increased modestly from 58.89 mA to 68.27 mA (16% increment), as shown in Figures 10a–c. For the depression process, the current varies from −92.60 µA to −1.00 µA for 250 m, −111.27 µA to −3.03 µA for 100 m, and −111.70 µA to −62.15 µA for 10 m of PW. A combined plot of normalized current for different PWs is presented in Figure 10d. From Figure 10e, the calculated NL factors are 0.72, 0.39, and 0.08 for PWs of 250, 100, and 10 m, respectively.

Figure 10

Figure 10. Synaptic learning behavior of the memristor framework under potentiation and depression mechanisms at pulse amplitude of ±0.8 V: (a) PW of 250 ms, (b) 100 ms, (c) 10 ms, (d) Combined normalized current plot at ±0.8 V with different PWs 250, 100, 10 ms, and (e) Normalized synaptic current behaviors at pulse amplitude of ±0.8 V with different PWs 250, 100, 10 ms to compute NL factor.

For a pulse amplitude of ±1.0 V, the current is increased from 110.10 mA to 321.2 mA, corresponding to a 191% increment for a PW of 250 m. At a PW of 100 m, the current is increased from 102.36 mA to 307 mA (200% increment), while at a PW of 10 m, the current is increased modestly from 97.20 mA to 118.94 mA (22% increment), as shown in Figures 11a–c. For the depression process, the current varies from −136.2 µA to −0.63 µA for 250 m, −138.49 µA to −1.28 µA for 100 m, and −138.98 µA to −63.55 µA for 10 ms PW. A combined plot of normalized current for different PWs is presented in Figure 11d. From Figure 11e, the calculated NL factors are 0.97, 0.46, and 0.13 for PWs of 250 m, 100 m, and 10 m, respectively. These findings reveal that the NL factor increases with increasing pulse amplitude and decreases with decreasing PW.

Figure 11

Figure 11. Synaptic learning behavior of the memristor framework under potentiation and depression mechanisms at pulse amplitude of ±1 V: (a) PW of 250 ms, (b) 100 ms, (c) 10 ms, (d) Combined normalized current plot at ±1 V with different PWs 250, 100, 10 ms, and (e) Normalized synaptic current behaviors at pulse amplitude of ±1 V with different PWs 250, 100, 10 ms to compute NL factor.

Furthermore, for a pulse amplitude of ±1.5 V, the current is increased from 315.82 mA to 819.81 mA, corresponding to a 159% increment for a PW of 250 m. At a PW of 100 m, the current is increased from 278.68 mA to 816.60 mA (193% increment), while at a PW of 10 m, the current is increased modestly from 249.10 mA to 361.35 mA (45% increment), as shown in Figures 12a–c. For the depression process, the current varies from −206.06 µA to −0.63 µA for 250 m, −205.30 µA to −9.61 µA for 100 m, and −205.65 µA to −53.50 µA for 10 m of PW. A combined plot of normalized current for different PWs is presented in Figure 12d. From Figure 12e, the calculated NL factors are 0.99, 0.93, and 0.22 for PWs of 250, 100, and 10 m, respectively.

Figure 12

Figure 12. Synaptic learning behavior of the memristor framework under potentiation and depression mechanisms at pulse amplitude of ±1.5 V: (a) PW of 250 ms, (b) 100 ms, (c) 10 ms, (d) Combined normalized current plot at ±1.5 V with different PWs 250, 100, 10 ms, and (e) Normalized synaptic current behaviors at pulse amplitude of ±1.5 V with different PWs 250, 100, 10 ms to compute NL factor.

To further explore the brain facilitation phenomenon, pulse-paired facilitation (PPF) is demonstrated under different pulse amplitudes, PW, and other influencing parameters as discussed previously. In the PPF, the second spike followed by the first spike with a time interval introduces a higher amount of current (Tang et al., 2022), which confirms that the PPF is the function of the time interval between two consecutive synaptic spikes and their amplitude. Herein, several PPF responses have been demonstrated as a function of the time interval between two pulses and the pulse amplitude, as well as the other memristor framework parameters.

To simulate the PPF for this memristor framework, the inter-pulse time interval (Δt) of 1 µs–50 µs is used for all the simulations. The relative change in the PPF is calculated using Equation 7 (Ismail et al., 2023);

$PPF\left(\%\right)=\frac{I_2}{I_1}\times 100(7)$

Here, $I_1$ and $I_2$ indicate the current response of the first and second peaks, respectively. The dependence of PPF on the pulse amplitude is simulated by varying from 1 to 5 V, as shown in Figure 13a. The $I_2$/ $I_1$ value decreases as the pulse interval (Δt) increases for all amplitudes (1–5 V), as shown in Figure 13a. The maximum PPF of ∼155% is achieved for the pulse amplitude of 5 V. However, for pulse amplitude varying from 1 V to 4 V, the ratio of $I_2$/ $I_1$ is lower than 100%, which signifies that the pulse amplitude is not efficient in inducing any significant amplification in the $I_2$. Similar findings are reported earlier, which suggested that the PPF of the memristor is the function of both PW and pulse amplitude (Hu et al., 2013). Hence, the results suggest that the defined memristor framework successfully emulates the PPF response of the memristor. Next, the impact of PW on PPF is simulated, as depicted in Figure 13b, wherein PWs of 1, 2, and 5 µs (at constant pulse amplitude of 5 V) are considered, which demonstrate a similar decreasing trend of PPF with increasing inter-pulse interval. However, an increase in PW further reduces the PPF response. In general, the increase in PW with high pulse amplitude provides more electrical energy to the device, suggesting more local conductive filament formation that supports the existing filament to become bigger, leading to higher $I_2$ current (Hu et al., 2013). This phenomenon depends on the internal state dynamics of the memristor and can be emulated by using this memristor framework. For further simulations, the pulse amplitude and PW are fixed at 5 V and 1 µs, respectively. The influence of the internal state variable X_int on PPF is depicted in Figure 13c. As X_int increases from 0 to 1, the PPF decreases for a lower pulse inter-pulse interval.

Figure 13

Figure 13. (a) PPF as a function of pulse amplitude, (b) PPF as a function of PW at the pulse amplitude of 5 V, (c) PPF as a function of X_int at the pulse amplitude of 5 V and PW of 1 µs, (d) PPF as a function of A_p at the pulse amplitude of 5 V, PW of 1 µs, and X_int of 0.2, (e) PPF as a function of x_p at the pulse amplitude of 5 V, PW of 1 µs, X_int of 0.2, and A_p of 3.0, (f) PPF as a function of a_p at the pulse amplitude of 5 V, PW of 1 µs, X_int of 0.2, A_p of 3.0, and x_p of 0.1, (g) PPF as a function of b₁ at the pulse amplitude of 5 V, PW of 1 µs, X_int of 0.2, A_p of 3.0, x_p of 0.1, and a_p of 2.5.

As stated earlier, as the initial state variable approached 1, the device attained the LRS, depicting the formation of a conductive path between the electrodes. Consequently, no further increase in the second pulse $I_2$ current is possible (Dutta et al., 2024). Following this, X_int is fixed at 0.2, and the effect of A_p is examined, as shown in Figure 13d. The PPF increases with A_p varying from 0.5 to 3, which can be attributed to the faster migration of ions/vacancies and accelerated filament formation. The impact of nonlinear damping of the state variable (x_p) is shown in Figure 13e. As x_p increases from 0.1 to 1, the PPF decreases. Next, the impact of a_p, which controls damping under positive bias, is illustrated in Figure 13f. At lower a_p values ranging from 0.5 to 2, the device fails to exhibit clear PPF behavior. Interestingly, when a_p is set to 2.5, the PPF increases, but it decreases again for higher a_p values. Finally, Figure 13g shows the effect of b₁ while keeping other parameters constant. The PPF increases as b₁ is varied from 0.5 to 2.5. Therefore, it is evident that the proposed memristor framework successfully emulates PPF responses under wide variations of parameters.

Moreover, STM, LTM, and the transition from STM to LTM and vice versa are the key characteristics in the memory and neuromorphic computing system. To implement the transition from STM to LTM, the current response under different numbers of pulses is captured, as shown in Figures 14a,b. Herein, the pulse amplitude is fixed at 1.0 V with a PW of 1 m and an inter-pulse interval of 1 m, while the decay constant is set to 5 m. Under these applied conditions, the excitatory postsynaptic current (EPSC) decays to 50% of its initial value within 3.39 m for a single pulse, while under 20 pulses, the EPSC requires ∼46.9 m to reach the same level. This extended retention time with increasing pulse count demonstrates the transition from STM-to-LTM and vice-versa (Kumar and Rani, 2025). Figure 14c illustrates the synaptic re-stimulation process, wherein the same (or higher) levels of potentiation and depression can be achieved under comparatively fewer electrical stimuli.

Figure 14

Figure 14. (a,b) Transition from STM to LTM and vice-versa under different numbers of pulses, and (c) Potentiation and depression processes along with the re-stimulation process.

In this process, 10 positive/negative pulses with an amplitude of ±0.5 V are initially applied to induce potentiation and depression, respectively. The PW is set to 10 m, and the decay constant is maintained at 10 m. The synaptic weight increased from 0% to 72% with 10 positive pulses and subsequently decayed to 21% after applying 10 negative pulses. During the re-stimulation process, another set of 10 positive pulses is applied, which further increases the synaptic weight to 90%, and the initial synaptic weight of 72% is recovered with only 8 pulses, as depicted in Figure 14b. In the third cycle, the same potentiation level is achieved with approximately 5 pulses. The obtained behavior closely resembles the biological learning, wherein synaptic re-learning occurs more efficiently, enabling faster recovery of previously acquired information (Chang et al., 2011b; Wang et al., 2012; Seo et al., 2011).

Lastly, the STDP characteristic is emulated by implementing four different Hebbian learning mechanisms, as depicted in Figure 15. Under STDP responses, the synaptic efficiency is strengthened/weakened by controlling the pre-and post-synaptic pulse activity. If the pre-synaptic fire just before the post-synaptic (Δt > 0), the synaptic connection is strengthened. Conversely, if the post-synaptic fire just before the pre-synaptic (Δt < 0), then the synaptic connection is weakened. The following mathematical Equations 8–13 are used to simulate the STDP behaviour (Rastogi et al., 2021; Song et al., 2000):

Figure 15

Figure 15. Demonstration of biological STDP behaviour: (a) Asymmetric Hebbian (ASH) learning, (b) asymmetric anti-Hebbian (ASAH) learning, (c) Symmetric anti-Hebbian (SAH) learning, and (d) Symmetric Hebbian (SH) learning. Here, inset-1 and inset-2 show the programming pulsing schemes.

For the Asymmetric Hebbian rule;

$\Delta w=+A.e^{\left(\frac{\Delta t}{+\tau }\right)}for\left(∆t<0\right)(8)$

$\Delta w=-A.e^{\left(\frac{-\Delta t}{-\tau }\right)}for\left(∆t>0\right)(9)$

For the Asymmetric Anti-Hebbian rule;

$\Delta w=-A.e^{\left(\frac{\Delta t}{-\tau }\right)}for\left(∆t<0\right)(10)$

$\Delta w=+A.e^{\left(\frac{-\Delta t}{+\tau }\right)}for\left(∆t>0\right)(11)$

For the Symmetric Anti-Hebbian rule;

$\Delta w=-A.e^{\left(-abs\left(\frac{\Delta t}{-\tau }\right)\right.}(12)$

For the Symmetric Hebbian rule;

$\Delta w=+A.e^{\left(-abs\left(\frac{\Delta t}{+\tau }\right)\right.}(13)$

Here, $\Delta w$ is the weight change, +A and -A are the amplitude factors, Δt is the time interval between the pre-and post-synaptic spike, and $\tau$ is the time constant. For simulating the STDP characteristics, the amplitude factor (A) is set to 2, and the time constant (τ) is chosen as 20 m. Herein, four different types of STDP rules, such as asymmetric Hebbian (see Figure 15a), asymmetric anti-Hebbian (see Figure 15b), symmetric anti-Hebbian (see Figure 15c), and symmetric Hebbian (see Figure 15d) learning rules, are implemented by utilizing the proposed memristor framework. The insets in Figures 15a,b represent the pulse design for the respective STDP rule. For the STDP processes, the positive (+2 V, PW = 1 m) and negative (−2 V, PW = 1 m) are used as the firing of pre- and post-synaptic junctions. From Figure 15a, an asymmetric Hebbian learning rule is simulated in which the pre-synaptic spike fires before the post-synaptic spike, which strengthens the synaptic efficiency. On the other hand, post-synaptic spike firing before the pre-synaptic spike causes depression or weakens the synaptic efficiency.

Next, the asymmetric anti-Hebbian learning rule is simulated in which the synaptic weight is depressed if Δt >0 and potentiated if Δt < 0. The synaptic weight gradually approaches zero with an increase in the time interval, indicating a weakening of synaptic connectivity. Moreover, both symmetric anti-Hebbian and symmetric Hebbian STDP rules are also simulated (see Figure 15c,d), wherein the synaptic weight is modulated by applying two voltage pulses of opposite polarity. All these implemented STDPs are in good agreement with biological synapse functionalities (Song et al., 2000; Bi and M Poo, 1998). Therefore, all four types of STDP learning rules have been successfully simulated using the memristor framework, demonstrating its potential for implementing neuromorphic computing systems.

Conclusion

In summary, a detailed parametric evaluation and in-depth neuromorphic computing functionalities have been implemented by using the experimentally validated memristor framework. The memristor framework comprehensively demonstrated the importance of various parameters and their impact on the resistive switching and neuromorphic computing capabilities of the memristor. Moreover, this work efficiently presents the overall range of each parameter, including applied voltage, initial value of the state variable, boundedness of the state variable, control parameter governing its rate of change, experimental fitting coefficients, exponential factors, and conductivity slope, in which the memristor framework exhibits perfect memristor properties. Notably, the outcomes revealed that parameters such as voltage, internal state variable (X_int), rate of change of the state variable (x_p), and conductivity slope parameter (b₁) have a significant impact on the switching response of the memristor. In particular, the conductivity slope parameter (b₁) for positive voltage polarity helps to enable multilevel switching with 50 distinct conductance states. Moreover, the proposed memristor framework is efficiently able to implement neuromorphic functionalities, including conductance tuneability, synaptic learning, PPF, STM, LTM, and transition from STM-to-LTM, synaptic re-stimulation, and STDP through Hebbian learning rules. Therefore, the presented theoretical memristor framework can be useful in the in-memory computation circuit hardware, low-voltage logic operation, pattern recognition, and neuromorphic computing.

Data availability statement

The original contributions presented in the study are included in the article/supplementary material, further inquiries can be directed to the corresponding authors.

Author contributions

AD: Methodology, Conceptualization, Validation, Data curation, Investigation, Writing – original draft, Resources, Writing – review and editing, Software, Visualization, Formal Analysis. SR: Visualization, Writing – review and editing, Validation, Supervision, Resources, Data curation, Formal Analysis. SK: Writing – review and editing, Investigation, Conceptualization, Resources, Validation, Visualization, Formal Analysis, Supervision, Methodology, Writing – original draft. TP: Project administration, Funding acquisition, Writing – review and editing, Formal Analysis, Supervision.

Funding

The author(s) declared that financial support was received for this work and/or its publication. AD would like to thank the IIT(ISM) Dhanbad for providing an institute teaching assistant fellowship for a PhD. SK would like to thank the Department of Science and Technology (DST), New Delhi, for the research grant via IFA23-ENG-375. SR would like to thank the Faculty Research Scheme (FRS) project no. MISC0085. TP would like to thank the EPSRC FORTE Programme (Grant No. EP/R024642/2) and the RAEng Chair in Emerging Technologies (Grant No. CiET1819/2/93) for providing financial support.

Conflict of interest

The author(s) declared that this work was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Generative AI statement

The author(s) declared that generative AI was not used in the creation of this manuscript.

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