In the original article, there were mistakes in Table 5, Comparison of event-based neural processors, as published. The area per neuron for the transistor channel was incorrectly provided as “4 cm2” and should be “–” (empty). The synaptic plasticity for true North was incorrectly provided as “STDP” and should be “No Plasticity.” The area per neuron for Loihi was incorrectly provided as “0.4 mm2” and should be “0.4 mm2*.” The corrected Table 5, Comparison of event-based neural processors, appears below.
Table 5
| Chip name | Technology | Process (nm) | Neurons type | #Neurons | #Synapse | Area per neuron | #Energy per event | Synaptic plasticity |
|---|---|---|---|---|---|---|---|---|
| MNIFAT | Mixed Signal | 500 | LIF/M-N | 6,120 | – | 1,495 μm2 | 360 pJ | Programmable |
| DeepSouth | Digital | 28 | LIF | 200K | – | – | No Plasticity | |
| Dynap-SEL | Mixed Signal | 28 | I&F | 1,088 | 78,080 | 20 μm2 | 2.8pJ | STDP |
| BrainScaleS | Mixed Signal | 180 | AdEx IF | 512 | 100K | 1,500 μm2 | 100pJ | Hebbian learning, STDP |
| 2DIFWTA | Analog | 350 | I&F | 2,048 | 28,672 | – | No Plasticity | |
| HiAER-IFAT board with 4 chips | Analog | 90 | I&F | 256K | 256M | 140 μm2 | 22 pJ | No Plasticity |
| Transistor-Channel | Analog | 350 | Floating Gate MOSFET | 100 | 30,000 | – | 10 pJ | STDP |
| Neurogrid | Mixed signal | 180 | Adaptive Quad IF | 65K | 100M | 1,800 μm2 | 31.2pJ | No Plasticity |
| TrueNorth | Digital | 28 | Adaptive Exp IF | 1M | 256M | 3,325 μm2 | 45pJ | No Plasticity |
| SpiNNaker | Digital | 130 | Programmable | 16K | 16M | – | 43nJ | STDP |
| Loihi | Digital | 14 | Adaptive LIF | 130K | 130M | 0.4 mm2* | 23.6 pJ | Epoch-based, STDP |
Comparison of event-based neural processors.
Neurosynaptic core area with each core implements 1,024 neural units.
The authors apologize for these errors and state that the do not change the scientific conclusions of the article in any way. The original article has been updated.
Summary
Keywords
neuromorphic engineering, large-scale systems, brain-inspired computing, analog sub-threshold, spiking neural emulator
Citation
Thakur CS, Molin JL, Cauwenberghs G, Indiveri G, Kumar K, Qiao N, Schemmel J, Wang R, Chicca E, Hasler JO, Seo J, Yu S, Cao Y, van Schaik A and Etienne-Cummings R (2019) Corrigendum: Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain. Front. Neurosci. 12:991. doi: 10.3389/fnins.2018.00991
Received
07 December 2018
Accepted
10 December 2018
Published
07 January 2019
Approved by
Frontiers in Neuroscience Editorial Office, Frontiers Media SA, Switzerland
Volume
12 - 2018
Updates
Copyright
© 2019 Thakur, Molin, Cauwenberghs, Indiveri, Kumar, Qiao, Schemmel, Wang, Chicca, Hasler, Seo, Yu, Cao, van Schaik and Etienne-Cummings.
This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) and the copyright owner(s) are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.
*Correspondence: Chetan Singh Thakur csthakur@iisc.ac.in
This article was submitted to Neuromorphic Engineering, a section of the journal Frontiers in Neuroscience
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