ORIGINAL RESEARCH article
Front. Neurosci.
Sec. Neuromorphic Engineering
Volume 19 - 2025 | doi: 10.3389/fnins.2025.1656892
This article is part of the Research TopicAdvancing Adaptive and Energy-Efficient Neuromorphic Computing for Real-Time Edge AI and RoboticsView all articles
Spike-based Time-domain Analog Weighted-sum Calculation Model for Extremely Low Power VLSI Implementation of Multi-layer Neural Networks
Provisionally accepted
- Kyushu Institute of Technology, Kitakyushu, Japan
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A time-domain analog weighted-sum calculation model is proposed based on an integrateand-fire-type spiking neuron model. The proposed calculation model is applied to multi-layer feedforward networks, in which weighted summations with positive and negative weights are separately performed and two timings proportional to the positive and negative ones are produced respectively in each layer. The timings are then fed into the next layers without their subtraction operation. We also propose very large-scale integrated (VLSI) circuits to implement the proposed model. Unlike conventional analog voltage or current mode circuits, the time-domain analog circuits use transient operation in charging/discharging processes to capacitors. Since the circuits can be designed without operational amplifiers, they can operate with extremely low power consumption. We designed a proof-of-concept (PoC) CMOS VLSI chip to verify weighted-sum operation with the same weights. Simulation results showed that the precision was above 4-bit, the energy efficiency for the weighted-sum calculation was 237.7 TOPS/W (Tera Operations Per Second Per Watt), more than one order of magnitude higher than that in state-of-the-art digital AI processors. Our model promises to be a suitable approach for performing intensive in-memorycomputing (IMC) of deep neural networks (DNNs) with moderate precision very energy-efficiently while reducing the cost of analog-digital-converter (ADC) overhead.
Keywords: time-domain analog computing, Weighted sum, Spike-based computing, deep neural networks, Multi-layer perceptron, Artificial Intelligence hardware, AI Processor
Received: 30 Jun 2025; Accepted: 14 Aug 2025.
Copyright: © 2025 Wang, Tamukoh and Morie. This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) or licensor are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.
* Correspondence: Quan Wang, Kyushu Institute of Technology, Kitakyushu, Japan
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