Original Research ARTICLE
Efficient Synapse Memory Structure for Reconfigurable Digital Neuromorphic Hardware
- 1Department of Creative IT Engieering, Pohang University of Science and Technology, South Korea
Spiking Neural Networks (SNNs) have high potential to process information efficiently with binary spikes and time delay information. Recently, dedicated SNN hardware accelerators with on-chip synapse memory array are gaining interest in overcoming the limitations of running software-based SNN in conventional Von Neumann machines. In this paper, we proposed an efficient synapse memory structure to reduce the amount of hardware resource usage while maintaining performance and network size. In the proposed design, synapse memory size can be reduced by applying presynaptic weight scaling. In addition, axonal/neuronal offsets are applied to implement multiple layers on a single memory array. Finally, a transposable memory addressing scheme is presented for faster operation of spike-timing-dependent plasticity (STDP) learning. We implemented a SNN ASIC chip based on the proposed scheme with 65 nm CMOS technology. Chip measurement results showed that the proposed design provided up to 200X speedup over CPU while consuming 53 mW at 100 MHz with the energy efficiency of 15.2 pJ/SOP.
Keywords: Spiking neural network (SNN), digital neuromorphic hardware, weight decomposition, on-chip learning, spike-timing dependent plasticity
Received: 31 Jul 2018;
Accepted: 23 Oct 2018.
Edited by:Runchun M. Wang, Western Sydney University, Australia
Reviewed by:Ulrich Rückert, Bielefeld University, Germany
James C. Knight, University of Sussex, United Kingdom
Copyright: © 2018 Kim, Koo, Kim and Kim. This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) and the copyright owner(s) are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.
* Correspondence: Prof. Jae-Joon Kim, Pohang University of Science and Technology, Department of Creative IT Engieering, Pohang, South Korea, email@example.com