ORIGINAL RESEARCH article

Front. Neurosci.

Sec. Neuromorphic Engineering

Volume 19 - 2025 | doi: 10.3389/fnins.2025.1599144

A Scalable Neural Network Emulator with MRAM-Based Mixed-Signal Circuits

Provisionally accepted
Jua  LeeJua Lee1,2Jiho  SongJiho Song2Hyeon Seong  ImHyeon Seong Im2Jonghwi  KimJonghwi Kim2Woonjae  LeeWoonjae Lee2Wooseok  YiWooseok Yi3Soonwan  KwonSoonwan Kwon3Byungsu  JungByungsu Jung3Joohyoung  KimJoohyoung Kim4Yoonmyung  LeeYoonmyung Lee2Jung-Hoon  ChunJung-Hoon Chun2*
  • 1Samsung (South Korea), Seoul, Republic of Korea
  • 2College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Gyeonggi, Republic of Korea
  • 3Samsung Advanced Institute of Technology (SAIT), Gyeonggi-do, Republic of Korea
  • 4Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium

The final, formatted version of the article will be published soon.

In this study, we present a mixed-signal framework that utilizes MRAM (Magneto-resistive Random Access Memory) technology to emulate behaviors observed in biological neural networks on silicon substrates. While modern technology increasingly draws inspiration from biological neural networks, fully understanding these complex systems remains a significant challenge. Our framework integrates multi-bit MRAM synapse arrays and analog circuits to replicate essential neural functions, including Leaky Integrate and Fire (LIF) dynamics, Excitatory and Inhibitory Postsynaptic Potentials (EPSP and IPSP), the refractory period, and the lateral inhibition. A key challenge in using MRAM for neuromorphic systems is its low on/off resistance ratio, which limits the accuracy of current-mode analog computation. To overcome this, we introduce a current subtraction architecture that reliably generates multi-level synaptic currents based on MRAM states. This enables robust analog neural processing while preserving MRAM's advantages, such as non-volatility and CMOS compatibility. The chip's adjustable operating frequency allows it to replicate biologically realistic time scales as well as accelerate experimental processes. Experimental results from fabricated chips confirm the successful emulation of biologically inspired neural dynamics, demonstrating the feasibility of MRAM-based analog neuromorphic computation for real-time and scalable neural emulation. challenges [2]. These circuits not only emulate the computational capabilities of individual neurons but also employ spiking representations for communication, learning, memory, and computation. However, despite their reliance on biological neural networks as a reference, our understanding of these complex systems remains limited.Research efforts have been actively directed toward capturing more detailed signals in biological neural networks. For instance, recent developments have introduced nano-electrode arrays [7] capable of recording signals in biological neural networks. These arrays allow for the cultivation of neural networks directly on the surface of an integrated circuit, establishing connections with neurons. These developments motivate the need for hardware platforms capable of real-time interaction with biological signals, operating at biologically realistic time scales, and supporting biologically meaningful behaviors such as the refractory period and lateral inhibition.

Keywords: analog neural network1, biological neural network2, refractory period3, lateral inhibition4, inhibitory post synaptic potential5

Received: 24 Mar 2025; Accepted: 14 May 2025.

Copyright: © 2025 Lee, Song, Im, Kim, Lee, Yi, Kwon, Jung, Kim, Lee and Chun. This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) or licensor are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.

* Correspondence: Jung-Hoon Chun, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, 2066 Seobu-ro, Gyeonggi, Republic of Korea

Disclaimer: All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors and the reviewers. Any product that may be evaluated in this article or claim that may be made by its manufacturer is not guaranteed or endorsed by the publisher.