Icy-Hot: Decoupled Compute Paradigm towards a General-Purpose Superconducting CPU Design

Tara Renduchintala^*Jonghyun LeeHaipeng ZhaMichael QiMurali Annavaram

• University of Southern California, Los Angeles, United States

Single Flux Quantum (SFQ) superconducting technology offers substantial performance and power efficiency advantages over conventional CMOS, especially as the benefits of Dennard scaling continue to diminish. As SFQ design tools and fabrication capabilities mature, SFQ-based computation is poised to become a leading candidate in the post-CMOS computing landscape. However, the design of SFQ CPUs presents two fundamental challenges. First, the Josephson Junction (JJ) budget must be kept low to ensure manufacturability. Second, the lack of dense, compact on-chip memory in SFQ remains a significant bottleneck. Preliminary analysis of a basic CPU design revealed that control structures—such as decoders and dependency checkers—consume a disproportionately large share of the JJ count. Meanwhile, modern software and CPU architectures rely heavily on substantial on-chip memory for components like branch predictors and caches. To address these constraints, we introduce Icy-Hot, a novel CPU architecture that granularly decouples pipeline stages to optimize JJ usage. Observing that SFQ-based execution ALUs are relatively JJ-efficient com-pared to memory and control logic, Icy-Hot places the execution stage within a 4K superconducting zone built entirely from SFQ circuits. The remaining pipeline stages—fetch, decode, and control—reside in a warmer 77K region implemented using conventional CMOS. Decoded instructions and control metadata are then passed from the Hot zone to the Icy zone for high-speed execution. We identify key architectural challenges in this hybrid design and propose solutions that combine compiler-inserted metadata with SFQ-specific circuit-level innovations. The Icy-Hot architecture effectively leverages the speed and efficiency of SFQ execution, while reducing JJ usage in memory and control logic through the integration of cryogenic CMOS. Our evaluation demonstrates a 38% power improvement over baseline designs, while consuming approximately 220,000 Josephson Junctions.