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REVIEW article

Front. Mater.

Sec. Semiconducting Materials and Devices

Volume 12 - 2025 | doi: 10.3389/fmats.2025.1618615

This article is part of the Research TopicAdvancing Superconducting Electronics for Server ApplicationsView all articles

Unconventional Compute Methods and Future Challenges for Superconducting Digital Computing

Provisionally accepted
George  MichelogiannakisGeorge Michelogiannakis*Anastasiia  ButkoAnastasiia ButkoPatricia  Gonzalez-GuerreroPatricia Gonzalez-GuerreroDilip  VasudevanDilip VasudevanMeriam  Gay Bautista-JurneyMeriam Gay Bautista-JurneyCarl  GraceCarl GracePanagiotis  ZarkosPanagiotis ZarkosJohn  ShalfJohn Shalf
  • Berkeley Lab (DOE), Berkeley, United States

The final, formatted version of the article will be published soon.

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

Keywords: Superconducting digital computing, logic families, Pulse trains, Race logic, Temporal computing, EDA tools, Sensors, Quantum control

Received: 26 Apr 2025; Accepted: 05 Aug 2025.

Copyright: © 2025 Michelogiannakis, Butko, Gonzalez-Guerrero, Vasudevan, Gay Bautista-Jurney, Grace, Zarkos and Shalf. This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) or licensor are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.

* Correspondence: George Michelogiannakis, Berkeley Lab (DOE), Berkeley, United States

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