Abstract
Two-dimensional electron gases (2DEGs) can be formed at some oxide interfaces, providing a fertile ground for creating extraordinary physical properties. These properties can be exploited in various novel electronic devices such as transistors, gas sensors, and spintronic devices. Recently several works have demonstrated the application of 2DEGs for resistive random-access memories (RRAMs). We briefly review the basics of oxide 2DEGs, emphasizing scalability and maturity and describing a recent trend of progression from epitaxial oxide interfaces (such as LaAlO3/SrTiO3) to simple and highly scalable amorphous-polycrystalline systems (e.g., Al2O3/TiO2). We critically describe and compare recent RRAM devices based on these systems and highlight the possible advantages and potential of 2DEGs systems for RRAM applications. We consider the immediate challenges to revolve around scaling from one device to large arrays, where further progress with series resistance reduction and fabrication techniques needs to be made. We conclude by laying out some of the opportunities presented by 2DEGs based RRAM, including increased tunability and design flexibility, which could, in turn, provide advantages for multi-level capabilities.
Introduction
Two-dimensional electron gases (2DEGs) can be formed at some oxides interfaces [1]. These oxide interfaces provided a fertile ground for the discovery and manipulation of extraordinary physics, such as superconductivity [2–5], magnetism [6, 7], magnetoelectric coupling [8, 9], Rashba spin-orbit coupling [10], persistent photoconductivity [11, 12], and integer/fractional quantum Hall effect [13, 14]. Over the last decade, leveraging these phenomena towards various devices, such as transistors [15–19], diodes [20], gas sensors [21], spintronic devices [22, 23], and memory devices [24–29], has drawn considerable attention. In addition to the exotic phenomena listed above, the emergence of a high sheet density of electrons (typically 1012∼1015 cm−2) between two insulators is already attractive for some devices, such as in the role of channels or back electrodes. We note that for the sake of convenience and simplicity, we very broadly use the term 2DEGs as a general name for conductive oxide interfaces, covering 2D, quasi-2D systems, and conducting interfaces where the dimensionality is not well-defined.
Oxide 2DEGs were first reported in epitaxial oxide interfaces, where a complex oxide such as LaAlO3 is grown, typically by pulsed laser deposition (PLD), on a single-crystal oxide substrate, typically SrTiO3 [1, 2] (Figure 1A). Therefore, forming such 2DEGs requires epitaxial oxide thin film deposition at high temperatures. Exploiting 2DEGs for novel electronic devices will significantly benefit from simplifying the materials and deposition methods, where low-temperature, scalable, and microelectronics-compatible approaches are of considerable advantage. Later work has demonstrated that 2DEGs can be formed at more simple interfaces, between amorphous and single-crystalline oxides [30, 31] with the benefit of room temperature preparation. Recently 2DEGs were shown to form even at amorphous/polycrystalline oxide interfaces [17, 21, 32, 33] (Figure 1C). Furthermore, the oxide deposition temperatures were reduced from 650-900°C to 25–300°C, and the deposition techniques have been extended from PLD to the more scalable atomic layer deposition (ALD), which is widely used by the microelectronics industry.
FIGURE 1
Among their various device prospects, recently, 2DEGs were utilized for resistive random-access memories (RRAMs) [24–28]. RRAM devices [34–36] are highly attractive for the next-generation memories [37, 38] and new computing paradigms [39–46]. The potential of 2DEGs in this role has yet to be critically discussed. In this mini review, we briefly review the oxide material systems hosting 2DEGs, focus on their application in the RRAM devices, and finally discuss the challenges and opportunities for 2DEGs in RRAM applications.
Two-Dimensional Electron Gases Formed at Oxide Interfaces
The 2DEG formed in the oxide material system was first observed at the atomically sharp interface between epitaxial LaAlO3 and single-crystalline SrTiO3 substrates, each insulating on its own [1, 2] (Figure 1A). In parallel to significant research into the fundamentals of this rich 2D system [47–49], 2DEGs were reported in dozens of other oxide combinations, such as GdTiO3/SrTiO3 [50] and NdTiO3/SrTiO3 [51].
The origin of the 2DEG formed at the LaAlO3/SrTiO3 interface was initially ascribed to polar discontinuity, commonly referred to as the “polar catastrophe”. The LaAlO3 film consisting of charge-alternating planes of LaO+ and AlO2− [52] is grown epitaxially on a TiO2-terminated SrTiO3 substrate. An electrostatic potential builds up in the LaAlO3 layer and increases with its thickness. As the thickness of the LaAlO3 film increases to four unit cells or higher, the voltage drop becomes sufficiently large for electrons to move from the surface of the LaAlO3 film to the LaAlO3/SrTiO3 interface, where they occupy delocalized Ti 3d states in SrTiO3 [52–56].
Besides the polar catastrophe mechanism, the ionic aspect of the interface plays an important role in its electronic properties [57]. Interdiffusion and intermixing of atoms across the interface [58] and oxygen vacancies [59–61] can account for the 2DEG formation via various ionic doping mechanisms. It is further argued that polar effects can drive such ionic mechanisms by making them more energetically favorable [62, 63]. These ionic features of the interface open opportunities to simplify the 2DEG material systems to non-polar, amorphous oxide materials. As such, the formation of 2DEG and their properties are strongly dependent on the material system, deposition method, and post-deposition processes.
The growth of epitaxial oxides requires slow and high-temperature (typically 650–900°C) processes using PLD or molecular-beam epitaxy (MBE). These features, and their low scalability (PLD), make the 2DEGs formed at epitaxial oxide interfaces incompatible with CMOS processes and large-scale fabrication. The use of amorphous oxide on single crystal oxide substrates [16, 24, 30, 31, 64–68] (Figure 1B) lowered the oxide deposition temperatures to <300°C and expanded the deposition methods to ALD. The use of amorphous oxides deposited on polycrystalline oxide [17, 21, 25, 32, 33, 69], which we term “All-ALD 2DEGs”, provides a great advantage towards scalability and integration with existing and future technologies (Figure 1C). We note that significant progress has been demonstrated in MBE-based integration of epitaxial oxide 2DEGs systems with silicon [70–72] and other semiconductors [73, 74]. Still, while potentially scalable [75], they remain slow, expensive, and high temperature (∼600°C) and thus fall far behind the non-epitaxial ALD approaches.
This chronological trend of simplifying the materials and fabrication techniques has seen the transition from epitaxial interfaces (e.g., single crystalline LaAlO3/single crystalline SrTiO3, Figure 1A) to amorphous oxides on single-crystals (e.g., a-LaAlO3/single crystalline SrTiO3, Figure 1B), and recently to All-ALD 2DEGs with amorphous-polycrystalline systems (e.g., amorphous Al2O3/polycrystalline TiO2, Figure 1C). The third system allows deposition temperatures to decrease to <300°C, well below the requirements of CMOS backend processes. Such advances hold the significant promise of realizing the potential of 2DEGs into practical devices and maturing them from single device lab-scale demonstrators towards scalable and microelectronics-compatible technology. In this mini review, we focus on the application of 2DEGs in RRAM devices.
Resistive Random-Access Memory Devices
The RRAM device has a simple metal-insulator-metal (MIM) structure with a resistive switching layer(s) sandwiched between two electrodes. It stores information by using different resistance states. For binary information storage, “0” and “1” information can be stored within one device cell using high and low resistance states (HRS and LRS, respectively). For multi-level information storage, more than a single bit of information can be stored within a single device cell using multiple resistance states. For example, information of “00”, “01”, “10”, and “11” can be stored within one device cell using four different resistance states. Besides information storage, RRAM devices are also promising for new computing paradigms [39–44], which are faster in speed and lower in energy consumption. The resistive switching processes can accompany typical physical/chemical effects such as electrochemical/thermochemical reactions or metal-insulator transitions [34, 36, 40]. In the conductive filament (CF)-type RRAM devices, the mechanism of the resistance switching is the formation and disruption of conductive filaments (nanometric in diameter) within the resistive switching layer (a few nanometers in thickness) under external electrical stimuli. RRAM devices have many attractive features, such as small device area (4 F2), fast switching speed (<1 ns) [76], high scalability [77–79], 3D integration capability [80, 81], and low energy consumption for resistance switching (<10 pJ/bit) [82, 83]. Based on the type of the conductive filaments, the RRAM devices can be divided into two types, which are the valence change memory (VCM) [76] and the electrochemical metallization memory (ECM) [84–86], which is also known as conductive-bridge RAM (CBRAM).
Two-Dimensional Electron Gases at Oxide Interfaces for Resistive Random-Access Memory Applications
Recently, 2DEGs have been leveraged for forming different types of RRAMs, by replacing one of the metal electrodes. This path can potentially increase design flexibility, enhance performance, and yield additional interesting properties.
In VCM devices, the 2DEG acts as an unconventional bottom electrode. In addition to the (electronic) conductivity of 2DEGs, their inherent ionic defects and instabilities can induce, interact with, and be utilized to control the resistive switching process. The oxide forming the 2DEG adjacent to the top electrode also acts as the resistive switching layer. The oxygen vacancies drift under the external electric field and create defect-induced gap states within the resistive switching layer during the resistive switching process. Whereas the electronic conduction property of 2DEGs performs as the function of a traditional metal bottom electrode. Several VCM RRAM devices have been recently reported, leveraging such 2DEG electrodes. These include Pt/LaAlO3/SrTiO3 [26], indium tin oxide (ITO)/LaAlO3/SrTiO3 [28], Pt/Ta2O5-y/Ta2O5-x/SrTiO3 [27], and Pt/Al2O3/SrTiO3 [24].
Wu et al. [26] were the first to use oxide 2DEGs in RRAM devices. Their device utilized the 2DEG formed at the epitaxial LaAlO3/SrTiO3 interface as the bottom electrode, the LaAlO3 layer as the resistive switching layer, and the Pt layer as the top electrode layer. The conduction mechanisms are Ohmic transport at the low resistance state (LRS) and tunneling at the high resistance state (HRS). The LaAlO3 layer was deposited on TiO2-terminated SrTiO3 (001) substrates using PLD at 800°C. The device switches based on the electric-field-induced drift of positively charged oxygen vacancies across the LaAlO3/SrTiO3 interface and the creation of defect-induced gap states within the ultrathin LaAlO3 layer. Wu et al. [28] further substituted the Pt top electrode with ITO and demonstrated an optically transparent RRAM device. After replacing the Pt with ITO, the resistance window remained at 100. In contrast, the overall resistance level increased by five orders of magnitude from HRS at 104 Ω and LRS at 102 Ω to HRS at 109 and LRS at 107 Ω. The Pt/LaAlO3/SrTiO3 and ITO/LaAlO3/SrTiO3 structured devices both showed 2000 cycle endurance and 12 h retention, comparable to those in the Pt/LaAlO3/Nb:SrTiO3 structured devices [87].
Joung et al. [27] reported amorphous TaOx/single crystal SrTiO3 based VCM. Ta2O5-y (TO2)/Ta2O5-x (TO1) bilayer of TaOx was deposited using PLD at 200°C under 70–100 mTorr oxygen (TO2) and at 700°C under 0.5 mTorr oxygen (TO1). The interface conductivity results from ionic defects formed during the high-temperature step and possibly kinetic damage from the PLD process. This use of amorphous layers constitutes progress toward simplifying the materials and deposition techniques. However, the PLD process’s high temperature and low scalability remain incompatible with practical applications. The devices showed 2000 cycles endurance and 105 s retention. The best endurance and retention of TaOx based RRAM devices are reported in Pt/Ta2O5-δ/TaO2-β/Pt structured devices [88] with 109 endurance cycles and 7.2 × 106 s retention.
Miron et al. [24] continued this trend of using amorphous layers for the 2DEG formation but focused on simple, low temperature, and scalable deposition. They reported amorphous Al2O3/single crystal SrTiO3 based VCM devices, where the Al2O3 layer was deposited using ALD, with a low deposition temperature of 300°C (Figure 2A). The devices showed a large OFF/ON resistance ratio of ∼106 and low operation currents down to 10−13 A (HRS, Figure 2B) with good cycle-to-cycle uniformity. The memory is based on the formation and rupture of oxygen vacancies filaments inside the Al2O3 layer. The oxygen vacancies driven from the interface into the insulating oxide under high electric fields are the key in enabling the resistive switching behavior. A key feature of this work is the application of low-defect Al2O3 [89], where the 2DEG serves as the bottom electrode and as the source of oxygen vacancies. The oxygen vacancies are injected by the electric field into the insulating Al2O3 to form the conductive filament. The practical consequence of this approach is the trigger of resistive switching behavior as compared to the Pt/Al2O3/Nb:SrTiO3 stuctured device [89] and a large OFF/ON resistance ratio afforded by using a good insulator of Al2O3 as the resistive switching layer and the 2DEG as the bottom electrode [24, 90, 91]. The key shortcoming here was the large set/reset voltages, on the order of ±7 V, another consequence of the insulating Al2O3. Further optimization of these devices, focusing on the insulator thickness, is expected to yield a better tradeoff between lowering the set/reset voltages while preserving the high OFF/ON resistance ratios.
FIGURE 2
As discussed earlier, All-ALD 2DEGs provide the most practical and scalable approach for 2DEG formation. Kim et al. [25] reported the first RRAM application of such 2DEGs, the only reported 2DEG CBRAM device (Figures 2C,D). They demonstrated a Cu conductive filament device based on 2DEG formed between amorphous Al2O3 and polycrystalline anatase TiO2 (Figure 1C). Both materials were fabricated by ALD (250°C) and, most importantly, without a crystalline substrate. The devices showed good endurance of 107 cycles and a high OFF/ON resistance ratio of 106. Four different HRS levels are also achieved by adjusting the amplitude of the operation voltage pulses. The LRS kept constant, whereas the HRS increased as the device areas decreased. This resistance and device area dependency is beneficial for device area scaling. A higher OFF/ON resistance ratio and a lower current level can be achieved as the device area becomes smaller. The Cu conductive filament formed at LRS, observed by TEM, is about 20 nm in diameter. A device diameter of 20 nm is, in principle, the area scaling limit of such a device. This device also showed better endurance and retention behavior than Cu/Al2O3/Pt structured devices [93, 94]. We highlight again the significant progress made by circumventing a single crystalline substrate, which allows integrating these devices on many substrates, such as the backend of silicon chips, flexible electronics [21], and others.
In more conventional VCM-type RRAM devices, the resistive-switching material typically contains some initial number of defects rearranged during the first forming process. A difference of 2DEGs-based VCM RRAM is that one can start with a fairly insulating material and use the 2DEG as an extrinsic source of defects [24]. This provides 2DEGs-based VCM RRAM with significantly larger OFF/ON resistance ratios compared to more conventional approaches. The high OFF/ON resistance ratio offers potential for multi-level resistance operation. The broader ratio provides more room for improvement of this feature, as more distinct states can fit this wider resistivity range [94]. However, multi-level behavior has yet to be reported in 2DEGs based VCM devices due to the abruptness of their switching. Another consequence of the high OFF/ON resistance ratio is extremely low current at HRS, which benefits low-power operation. A comparison of 2DEG based RRAM devices, devices that show close similarity to the 2DEG based device structures, and some other RRAM devices are listed in Table 1.
TABLE 1
| Device Structure | Device Size | Forming (Yes/No, Vforming, Icc) | Top electrode | Resistive switching layer | Bottom electrode | Switching polarity | SET/RESET Voltage (DC) | Max Iset/ICC (DC) | Max Ireset (DC) | SET/RESET Voltage (AC) | SET/RESET Switching speed (AC) | HRS/LRS (Ω) | Resistance ratio | Endurance (cycles) | Retention (s) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Pt/LaAlO3/SrTiO3 [26] | 2.25 × 104 μm2 | Yes, -4 V, 30 mA | Pt | LaAlO3 | LaAlO3/SrTiO3 2DEG | bipolar | −4 V/+4 V | 30 mA/No ICC | 30 mA | −4 V/+4 V | 5 ns/100 μs | 104/102 | 102 | 2000 | >4.32 × 103 (@25°C) |
| −4 V/+9 V | 5 ns/1 μs | ||||||||||||||
| ITO/LaAlO3/SrTiO3 [28] | 9 × 104 μm2 | Yes, -3.3 V, 30 μA | ITO | LaAlO3 | LaAlO3/SrTiO3 2DEG | bipolar | −1.5 V/+5 V | 30 μA/No ICC | 0.5 nA | −5 V/+5 V | Not given | 109/107 | 102 | 2000 | >4 × 104 (@25°C) |
| Pt/LaAlO3/Nb:SrTiO3 [87] | 106 to 104 μm2 | Yes, -13 V to -40 V (PO2 and tox dependent), ICC not given | Pt | LaAlO3 | Nb: SrTiO3 | bipolar | −6 V/+6 V | 70 mA/no ICC | 10 mA | −8 V/+8 V | Not given | 106/103 | 103 | 2000 | >4.32 × 103 (@25°C) |
| ITO/LaAlO3/ITO [94] | 1.13 × 106 μm2 (⌀ = 1,200 μm) | Yes, -1 V to -2.6 V (PO2 dependent), 10 mA | ITO | LaAlO3 | ITO | bipolar | Not given/+3 V | Not given | 5–10 mA | Not given | Not given | 103/102 | 10 | 100 | Not given |
| Pt/Ta2O5-y/Ta2O5-x/STO [27] | 490.63 μm2 (⌀ = 25 μm) | Not mentioned | Pt | Ta2O5-y | Ta2O5-x/STO 2DEG | bipolar | +4 V/−2.5 V | 2 μA/no ICC | 1 μA | Not given | Not given | 1012/108 | 104 | 2,900 | >105 (@25°C) |
| Pt/Ta2O5-δ/TaO2-β/Pt [88] | 0.25 μm2 | Not mentioned | Pt | Ta2O5-δ/TaO2-β | Pt | bipolar | −0.9 V/+2 V | 170 μA/170 μA | 170 μA | 2 V/−1.5 V | 10 ns | 103/102 | 10 | 109 | 1.08 × 107 (@150°C) |
| Pt/Al2O3/STO [24] | 2.7 × 104 to 1.5 × 105 μm2 | Yes, -6 V to −4 V, 0.1 mA | Pt | Al2O3 | Al2O3/STO 2DEG | bipolar | −7 V/+7 V | 0.5 mA/not mentioned | 0.5 mA | Not given | Not given | 1010/104 | 106 | 100 | Not Given |
| Pt/Al2O3/Nb:SrTiO3 [89] | No resistive switching behavior | ||||||||||||||
| Pt/Al2O3/TiN [90] | 2.5 × 10−3 μm2 | Yes, 7 V, <10 μA, no ICC | Pt | Al2O3 | TiN | Bipolar | +3 V/−2 V | <300 μA/300 μA | <1 mA | 8 V/−4 V | 10 ns/10 ns | 106/103 | 103 | 1,000 | Not given |
| Ni/Al2O3/Pt [90] | 104 μm2 | Yes, 5 V, 500 μA | Ni | Al2O3 | Pt | Bipolar | +1.2 V/−0.45 V to −0.6 V | 500 μA/500 μA | <2 mA | 1.5 V/−0.4 V to −0.58 V | 5 ms/5 ms | 2.8 × 103 to 2.2 × 103/470 | 6 to 4.7 | 100 | 103 s |
| Cu/Al2O3/TiO2 [25] | 0.02–340 μm2 | Yes, 1 to 5V, no Icc (self-compliance), Imax<0.1 mA | Cu | Al2O3 | Al2O3/TiO2 2DEG | bipolar | +3 V/−5 V | <0.1 mA/no ICC (self-compliance) | <0.1 mA | Not given | 500–800 ns | 1011/105 | 106 | 107 | 106 (@85°C) |
| Cu/Al2O3/Pt [92] | 3.14 × 104 μm2 (⌀ = 200 μm) | Yes, 8 V, 200 μA | Cu | Al2O3 | Pt | bipolar | 0.3–1.2 V/-0.1 V to −0.7 V | 150 μA/150 μA | <0.1 mA | Not given | Not given | 109/103 | 106 | 2000 | 105 |
| Cu/Ti/Al2O3/Pt [93] | 0.05 μm2 (via hole ⌀ = 0.25 μm) | Yes, 1.1 V, 200 μA | Cu/Ti | Al2O3 | Pt | bipolar | 0.3–0.7 V/−0.1 V to −0.3 V | 200 μA/200 μA | ∼0.1 mA | Not given | Not given | 109/104 | 105 | Not given | 104 |
| Pt/WOx/W [96] | 2 × 10−3 μm2 | No, Forming free | Pt | WOx | W | bipolar | 1 V/−1 V | 4 mA/no ICC | <0.2 mA | +1.25 V/-1 V | 5 μs/5 μs | 106/104 | 102 | 107 | Not Given |
| IrOx/Al2O3/TiOx/TiN [97] | 0.24 μm2 | Yes, 7.5–20 V, 100 μA | IrOx | Al2O3 (2–8 nm)/TiOx | TiN | bipolar | 3.5–5.4 V/−3 V | 100 μA/100 μA | <15 μA | +3 V−5.5 V/-3 V | 500 μs/10 ms | 4 × 106 to 107/0.4 × 106 to 1.2 × 106 | 10.8 to 21.62 | 105 to 106 | Not Given |
| TiN/Ti/TiO2-x/TiO2-y/Au [98] | 104 μm2 | No, Forming free | TiN/Ti | TiO2-x/TiO2-y | Au | bipolar | 3 V/−3 V | <0.1 mA/No ICC (self-compliance) | <0.1 μA | +8 V/−8 V | 10 ms/10 ms | 8 × 108 to 4 × 1010/6 × 105 to 5 × 108 | 2 to 3.6 × 103 | Not Given | Not Given |
| Ru/TiO2−x/HfO2/Ru [99] | 104 μm2 | Yes, 4–4.5 V, 5 mA | Ru | TiO2−x/HfO2 | Ru | bipolar | 2 V/−1.5 V | 5 mA/5 mA | <5 mA | Not given | Not given | 103/102 | 10 | 104 | 105 |
| Ni/GeO/SrTiO3/TaN [100] | 11304 μm2 | Not given | Ni | GeO/SrTiO3 | TaN | bipolar | −0.3 V to −1.2 V/0.13–0.3 V | 3.5 μA/No ICC (self-compliance) | 0.12 nA | −1.5 V/0.5 V | 50 ns/50 ns | 1012/106 | 106 | 106 | 4 × 105 (@85°C) |
Comparison of device performances.
We consider the progress made with the All-ALD 2DEGs [25, 33] to be a defining point. The All-ALD 2DEGs have liberated 2DEGs from small and expensive single-crystal substrates and from costly high-temperature fabrication processes. 2DEGs are now being fabricated by ALD on many substrates while keeping a low thermal budget and using low-cost, highly scalable, mature, and microelectronics-compatible techniques. The use of anatase TiO2 provides another advantage of a potentially more conductive 2DEG compared to the LaAlO3/SrTiO3 interface at room temperature [64] and offers tunability of the conductivity [32, 33]. Higher conductivity of the 2DEG is desirable in RRAM applications because the resistance of the bottom electrode is in series with the resistive switching layer, making lower resistance beneficial for stabilizing the resistive switching behavior, and for reducing the operating power. These issues become more important when considering integrating devices into a crossbar structure.
Challenges
The 2DEGs based RRAM devices reported so far are all single device demonstrations. Integration of the 2DEGs based RRAM devices into a crossbar array or 3D vertical structures poses an open challenge, which requires several issues to be addressed. Due to their high series resistance, the relatively high sheet resistance of many 2DEGs (typically >104 Ω/□) makes it challenging to utilize 2DEGs as thin line bottom electrodes. Beyond increasing the operating voltage (and power), this series resistance of the bottom electrode could further cause a significant spatial distribution of operation voltages across a crossbar array. As such, it remains an important task to reduce the 2DEG resistivity and design new device structures for high-density RRAM integration. Another facet of these challenges is microfabrication: 2DEGs, particularly those driven by defects, can be challenging to pattern efficiently [101–103]. Robust fabrication techniques need to be designed to produce the small features necessary for high-density RRAM arrays. In addition, further flexibility in the tuning of the 2DEG resistivity would provide an advantage for device and array optimization, which would further benefit from a deeper understanding of the 2DEGs-based RRAM switching mechanisms.
Opportunities
As discussed earlier, 2DEGs-based RRAMs can feature large, potentially tunable OFF/ON resistance ratios. These provide prospects of low power operation, allow additional “room” for efficient multi-level resistance states, and provide additional design flexibility and tunability compared to some of the current devices. The 2DEGs-based VCM devices so far all showed abrupt switching processes, resulting in binary resistance states. Further development of these devices into multi-level capabilities will provide considerable functionality benefits. Since 2DEGs are successfully applied as the channel of transistors [15, 16, 19, 32]. This opens routes for integrating both the memory and the peripheral circuits within the same material system and even within the same lithography process steps. This is also a very attractive feature for RRAM devices in crossbar arrays since the crossbar structured RRAM devices require selectors to select different rows and columns.
Statements
Author contributions
All authors discussed and designed the structure and scope of the mini-review, which was written by YL. All authors read and commented on the text.
Acknowledgments
YL and LK acknowledge the support of the Israeli Science Foundation (ISF Grant 375/17). YL acknowledges the support from a Technion Fellowship. The authors acknowledge discussions with Wei Wang and his inputs to the manuscript.
Conflict of interest
The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.
Publisher’s note
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Summary
Keywords
oxide interfaces, resistive random-access memories, device physics, oxide electronics, oxide electronic devices
Citation
Li Y, Kvatinsky S and Kornblum L (2021) Harnessing Conductive Oxide Interfaces for Resistive Random-Access Memories. Front. Phys. 9:772238. doi: 10.3389/fphy.2021.772238
Received
07 September 2021
Accepted
11 October 2021
Published
27 October 2021
Volume
9 - 2021
Edited by
Ayan Roy Chaudhuri, Indian Institute of Technology Kharagpur, India
Reviewed by
Writam Banerjee, Pohang University of Science and Technology, South Korea
Nagarajan Raghavan, Singapore University of Technology and Design, Singapore
Amit Prakash, Crossbar inc., United States
Updates
Copyright
© 2021 Li, Kvatinsky and Kornblum.
This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) and the copyright owner(s) are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.
*Correspondence: Yang Li, liyang.leonlee@gmail.com; Lior Kornblum, liork@ee.technion.ac.il
This article was submitted to Interdisciplinary Physics, a section of the journal Frontiers in Physics
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