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ORIGINAL RESEARCH article

Front. Mater., 12 December 2025

Sec. Semiconducting Materials and Devices

Volume 12 - 2025 | https://doi.org/10.3389/fmats.2025.1735405

This article is part of the Research TopicOxide Semiconductor Devices and ApplicationsView all articles

Enhanced electrical stability of IGZO thin-film transistors using atomic layer deposited Al2O3/HfO2 dual-layer gate insulator

Shaocong LvShaocong Lv1Weilin WangWeilin Wang1Shuaiying ZhengShuaiying Zheng1Chengyuan WangChengyuan Wang1Qian XinQian Xin1Yuxiang LiYuxiang Li1Aimin Song,Aimin Song2,3Jaekyun KimJaekyun Kim4Jidong Jin
Jidong Jin4*Jiawei Zhang
Jiawei Zhang1*
  • 1Shandong Technology Center of Nanodevices and Integration, School of Integrated Circuit, Shandong University, Jinan, China
  • 2Institute of Nanoscience and Applications, Southern University of Science and Technology, Shenzhen, China
  • 3Department of Electrical and Electronic Engineering, University of Manchester, Manchester, United Kingdom
  • 4Department of Photonics and Nanoelectronics, Hanyang University, Ansan, Republic of Korea

This study investigates the stability of positive bias temperature stress (PBTS) in bottom-gate indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) incorporating atomic layer deposited Al2O3/HfO2 dual-layer gate insulators (GIs). By optimizing the thicknesses of the Al2O3 and HfO2, hydrogen diffusion from the GI into the IGZO layer is effectively controlled and electron traps at the IGZO/GI interface are mitigated. The optimal dual-layer GI configuration for IGZO TFTs is identified as 15 nm Al2O3 on 5 nm HfO2, resulting in an exceptionally low threshold voltage shift of −0.02 V under PBTS at 125 °C for 104 s. Additionally, the device exhibits excellent electrical performance, with a saturation mobility of 11.61 cm2/Vs, a subthreshold swing of 114 mV/dec, and a threshold voltage of −0.23 V. These results highlight the potential of IGZO TFTs with dual-layer GIs for advanced integrated circuit applications.

1 Introduction

Indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) have attracted significant attention for various display applications due to their high carrier mobility, large-area uniformity and low-temperature processability (Ide et al., 2019; Shim et al., 2020; Shi et al., 2021; Geng et al., 2023; Çeliker et al., 2024; Bao et al., 2025). Furthermore, IGZO TFTs have demonstrated compatibility with back-end-of-line (BEOL) processes, making them suitable for integration into complex integrated circuits (Chi et al., 2016; Yu et al., 2016; Duan et al., 2022; Izukashi et al., 2025).

High-k dielectric materials, such as Al2O3 (Ma et al., 2018a), HfO2 (Ma et al., 2018b), Ta2O5 (Chiu et al., 2010) and ZrO2 (Lee et al., 2010) have been employed as gate insulators (GIs) to enable low-voltage operation in IGZO TFTs while maintaining good device performance. The choice of high-k dielectrics significantly impacts the electrical performance of IGZO TFTs, particularly in terms of leakage currents, interface quality and driving current capability (Lee et al., 2013; Geng et al., 2014; Li et al., 2022). In addition to the impact of high-k dielectrics on electrical characteristics, device reliability under bias stress must be rigorously evaluated. For BEOL compatible IGZO TFTs in integrated circuit applications, positive bias temperature stress (PBTS) is a critical metric for assessing device reliability (Kim et al., 2023; Kim et al., 2024). Therefore, ensuring high PBTS stability is essential for the development of robust and efficient integrated circuit technologies.

Both electron trapping at the IGZO/GI interface and hydrogen (H) diffusion from the GI into the IGZO channel strongly influence device reliability of IGZO TFTs under PBTS (Kim et al., 2023; Kim et al., 2024; Liu et al., 2024b). Notably, the H content in the GI critically affects PBTS stability (Kim et al., 2024; Lin et al., 2024; Liu et al., 2024a; Liu et al., 2024b; Lv et al., 2025). Under PBTS, it should be noted that high H content in the GI can diffuse into the IGZO channel and form donor-like states (Kim et al., 2024; Liu et al., 2024b). These states increase free electron density and passivate IGZO/GI interface defects, leading to negative threshold voltage shifts (ΔVTH) (Kim et al., 2024; Liu et al., 2024b; Lv et al., 2025). In contrast, low H content in the GI may leave IGZO/GI interface traps unpassivated under PBTS, resulting in positive ΔVTH (Kim et al., 2024; Lv et al., 2025). Therefore, precise control of H concentration in the GI is essential for achieving reliable PBTS stability with minimal ΔVTH.

In this study, we introduce a H-regulated GI strategy for IGZO TFTs, enabled by an engineered Al2O3/HfO2 dual-layer stack that precisely modulates H diffusion and electron trapping dynamics. The H content in the GI was controlled by adjusting the thickness of HfO2 and Al2O3 during the atomic layer deposition (ALD) process. Through combined PBTS measurements, X-ray photoelectron spectroscopy (XPS) and time-of-flight secondary ion mass spectrometry (TOF-SIMS) analyses, we identified H concentration and transport pathways within the GI as the primary factors governing the direction and magnitude of ΔVTH for IGZO TFTs under PBTS. It was found that the device based on a 15 nm Al2O3/5 nm HfO2 dual-layer GI effectively passivate electron traps at the IGZO/GI interface without inducing significant H diffusion under PBTS. As a result, the device demonstrates excellent PBTS stability with a ΔVTH of −0.02 V at 125 °C for 104 s. Furthermore, the device demonstrated excellent electrical performance. These characteristics demonstrate that this approach offers a promising pathway toward IGZO TFTs with both high stability and excellent electrical performance for display and integrated circuit technologies.

2 Experimental section

Figure 1a illustrates the schematic diagram of bottom-gate IGZO TFTs with different GIs: 20 nm Al2O3 (Device 1), 20 nm HfO2 (Device 2), 10 nm Al2O3/10 nm HfO2 (Device 3), and 15 nm Al2O3/5 nm HfO2 (Device 4). Initially, a 50-nm-thick W gate electrode was deposited on the SiO2/Si substrate by radio-frequency (RF) sputtering at room temperature in an Ar atmosphere. Then, ALD was employed to deposit the GI materials at 200 °C. Trimethylaluminum (TMA) and tetrakis(dimethylamido)hafnium (TDMAH) served as the precursors for Al2O3 and HfO2 respectively, with H2O used as the oxidant. Following the GI deposition, a 12 nm IGZO active channel layer was deposited by RF sputtering using an IGZO target with an In:Ga:Zn ratio of 2:2:1 at room temperature in Ar. Subsequently, the GI and IGZO channel layers were annealed at 400 °C for 1 h in O2. A 100 nm SiO2 passivation layer was then deposited by plasma-enhanced chemical vapor deposition (PECVD), and the source/drain regions were defined by reactive ion etching. The source and drain electrodes, consisting of 10 nm indium tin oxide and 100 nm tungsten, were deposited by RF sputtering. Finally, the IGZO TFTs underwent a post-deposition annealing at 400 °C for 1 h in O2. The channel width and length of the TFTs were 35 μm and 5 μm, respectively.

Figure 1
Diagram (a) shows a layered structure of a transistor with labeled components: source, drain, gate, substrate, SiO₂, IGZO, and GI. Each layer is associated with various devices showing different compositions and thicknesses of Al₂O₃ and HfO₂. Image (b) is a cross-sectional electron microscope view of the transistor highlighting layers of SiO₂, IGZO, Al₂O₃, HfO₂, WOₓ, and W. Image (c) displays an elemental map of the transistor layers, indicating presence of tungsten, hafnium, aluminum, indium, gallium, zinc, silicon, and oxygen.

Figure 1. (a) Schematic of IGZO TFTs with different dielectric layers. (b) Cross-sectional TEM image and (c) EDS image of Device 4.

Electrical characteristics were measured using a Keysight B2902A semiconductor parameter analyzer. PBTS tests were conducted in a chamber probe station with a hot chuck at both 25 °C and 125 °C. XPS spectra were recorded using a ThermoFisher ESCALAB 250Xi system. The spatial distribution of H was determined by TOF-SIMS depth profiling using an ION TOF-SIMS 5 instrument. The cross-sectional transmission electron microscopy (TEM) image and energy dispersive spectroscopy (EDS) elemental line scans were obtained using a high-resolution TEM (HRTEM, Talos F200X, Thermo Fisher Scientific).

3 Results and discussion

Figure 1b shows the cross-sectional TEM image of Device 4, revealing uniform, well-defined interfaces between all layers. Figure 1c shows EDS mapping of W, Hf, Al, In, Ga, Zn, Si, and O for Device 4, confirming uniform growth and distribution of all elements.

Figure 2a shows the capacitance densities of various dielectric materials measured using a metal-insulator-metal (MIM) device structure. The capacitance densities for 20 nm Al2O3, 20 nm HfO2, 10 nm Al2O3/10 nm HfO2, and 15 nm Al2O3/5 nm HfO2 are 334.16, 873.18, 483.34, and 395.14 nF/cm2, respectively. Figure 2b presents the transfer curves of the IGZO TFTs with different GIs, while Figures 2c–f show the corresponding output curves. Key device parameters, including threshold voltage (VTH), subthreshold swing (SS), field-effect saturation mobility (μsat), and interface trap density (Dit), were extracted from the transfer curves and are summarized in Table 1. The μsat and SS were calculated using the following Equations 1, 2 (Lee and Chung, 2023):

μsat=2LWCoxdIDdVG2(1)
SS=dlogIDdVG|max-1(2)

where L is the channel length, W is the channel width, Cox is the gate capacitance per unit area, ID and VG are the drain current and gate voltage, respectively. The VTH was defined at a drain current of (W/L) × 10 nA. The Dit can be estimated using the following Equation 3 (Jin et al., 2023):

Dit=SSlogekT/q-1Coxq2(3)

where k is the Boltzmann constant, T is temperature, and q is the elementary charge. When comparing single-GI devices, Device 2 (20 nm HfO2) shows a more positive VTH (−0.10 V) and higher Dit (4.22 × 1012 cm-2/eV) than Device 1 (20 nm Al2O3), while its μsat is slightly reduced due to the higher Dit. Devices 3 and 4, which employ Al2O3/HfO2 bilayer GIs, exhibit intermediate VTH and SS values, while maintaining high μsat (∼11.6 cm2/Vs) and relatively low Dit (∼2.2 × 1012 cm-2/eV), demonstrating that bilayer GIs can effectively balance VTH control, SS, and interface quality. To assess reproducibility, 5 additional devices of each type were tested, and the results are summarized in Figure 3, showing consistent device performance across samples.

Figure 2
Six graphs display electrical characteristics of different devices. (a) Capacitance vs. applied voltage for five dielectric stacks, with consistent capacitance from -2 to 4 V. (b) Drain current \(I_D\) vs. gate voltage \(V_G\) at \(V_D = 3.3\) V for four devices, showing varying thresholds. (c)-(f) Output characteristics for Devices 1 to 4, respectively, with \(I_D\) vs. drain voltage \(V_D\) at \(V_G\) from -0.2 to 3.3 V in steps of 0.5 V. Each device graph shows current increasing with higher gate voltage.

Figure 2. (a) Capacitance-voltage characteristics of MIM devices with different insulators. (b) Transfer characteristics of IGZO TFTs. Output characteristics of. (c) Device 1, (d) Device 2, (e) Device 3 and (f) Device 4.

Table 1
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Table 1. Electrical characteristics of IGZO TFTs with different GIs.

Figure 3
Scatter plot comparing four devices on three metrics: saturation mobility (\( \mu_{sat} \), black, left axis), threshold voltage (\( V_{TH} \), red, right axis), and subthreshold swing (SS, blue, right axis). Each device shows different values and error bars for each metric.

Figure 3. Statistical data of μsat, VTH, and SS of IGZO TFTs.

In addition to electrical performance, the reliability of these devices under PBTS was further evaluated, revealing distinct behaviors depending on the GI configuration, with Device 4 exhibiting the highest PBTS stability. The PBTS test results are shown in Figures 4a–d. During the PBTS measurements, a gate-stress voltage, VG (stress) = VTH + 2 V, was applied for 104 s under vacuum conditions at both 25 °C and 125 °C. The transfer curves were measured at VD = 0.05 V. The devices exhibit distinct behaviors under PBTS conditions, depending on the type of GI. Device 1 shows a positive ΔVTH of +0.1 V at 125 °C, indicating that electron trapping at the IGZO/Al2O3 interface or within the Al2O3 layer is the dominant degradation mechanism (Kim et al., 2023). In contrast, Device 2 exhibits a negative ΔVTH of −0.2 V under identical conditions due to excessive free carrier generation in IGZO, likely caused by H diffusion from the HfO2 GI (Lee et al., 2023). In Devices 3 and 4, which utilize a dual-layer GI, lower ΔVTH values were observed under PBTS at 125 °C for 104 s. Device 3 exhibits a ΔVTH of −0.07 V, while Device 4 exhibits a ΔVTH of −0.02 V. These enhanced PBTS stabilities suggest that the implementation of a dual-layer GI can effectively mitigate electron trapping at the IGZO/GI interface through H diffusion. For effective H diffusion, the H content must differ significantly between the two layers of the dual-layer GI. The variations in ΔVTH for IGZO TFTs with different GIs under PBTS at 125 °C are presented in Figure 4e. Clearly, Device 4 shows the best PBTS stability. Figure 4f illustrates the ΔVTH values measured at both 25 °C and 125 °C for IGZO TFTs with different GIs subjected to PBTS for 104 s, with Device 4 exhibiting the smallest variation in ΔVTH.

Figure 4
Graphs showing electrical behavior of four devices at 125°C. Graphs (a) to (d) display current (I\_D) vs. gate voltage (V\_G) with stress times. Device 1 shows ΔV\_TH = +0.1V, Device 2 ΔV\_TH = -0.2V, Device 3 ΔV\_TH = -0.07V, and Device 4 ΔV\_TH = -0.02V. Graph (e) plots threshold voltage shift (ΔV\_TH) against stress time, comparing all devices. Graph (f) compares ΔV\_TH for two temperatures (25°C and 125°C) across devices.

Figure 4. Variations in transfer curves with the evolution of stress time for (a) Device 1, (b) Device 2, (c) Device 3 and (d) Device 4 under PBTS (125 °C). Summary of (e) stress-time-dependent variations in ΔVTH and (f) ΔVTH at 104 s under 25 °C and 125 °C.

The chemical bonding states at the surfaces of HfO2 and Al2O3 gate dielectrics were examined using XPS. Figure 5 illustrates the O 1s core-level XPS spectra for both the HfO2 and Al2O3 films, where OI represents the metal–O bond, while OII represents the metal–OH bond. The area ratios of–OH in the HfO2 and Al2O3 films are 22.5% and 7.9%, respectively, indicating a significantly higher H content in the HfO2 film. Figure 6 presents TOF-SIMS analysis of the devices, revealing that the H intensity in HfO2 reaches 1.69 × 103 a.u., approximately four times higher than in Al2O3. For the devices with a dual-layer Al2O3/HfO2 GI, a pronounced H gradient is clearly observed across the interface.

Figure 5
X-ray photoelectron spectroscopy (XPS) spectra comparing aluminum oxide (Al₂O₃) and hafnium oxide (HfO₂). Graph (a) shows Al₂O₃ with measured and fitted curves indicating 92.1% Al-O and 7.9% Al-OH binding. Graph (b) shows HfO₂ with measured and fitted curves indicating 77.5% Hf-O and 22.5% Al-OH binding. Both graphs display intensity against binding energy in electron volts (eV).

Figure 5. The XPS spectra of (a) Al2O3 film and (b) HfO2 film with a thickness of 20 nm.

Figure 6
Graph depicting intensity versus sputtering time for four devices labeled in different colors: green (Device 1), blue (Device 2), red (Device 3), and gray (Device 4). Intensity is plotted on a logarithmic scale. The layers in the diagram, from left to right, are SiO2, IGZO, GI, and W. The graph shows varying intensity patterns across devices, with peaks near 100 seconds.

Figure 6. TOF-SIMS depth profiles of the intensities of H across the samples with different GIs.

Figure 7 presents the schematic energy band diagrams of IGZO TFTs incorporating different GI configurations under PBTS, constructed from the combined PBTS, XPS and TOF-SIMS analyses. The distinct PBTS behaviors observed across the devices can be directly attributed to differences in the H content of the Al2O3 and HfO2 layers. Figure 7a represents Device 1 (single Al2O3 GI) and indicates that the markedly low H concentration in the Al2O3 GI suppresses H-related reactions (Lv et al., 2025). As a result, electron trapping at the IGZO/GI interface or within the GI becomes the dominant PBTS mechanism, yielding a positive ΔVTH. under PBTS (Kim et al., 2024; Lv et al., 2025). In Figure 7b, representing Device 2 (single HfO2 GI), the significantly higher H concentration in the HfO2 GI promotes H diffusion from HfO2 into the IGZO channel. This migrated H acts as a shallow donor and increases the free electron density (Lee et al., 2023), leading to donor-generation-dominated and a negative ΔVTH. Figures 7c,d correspond to Devices 3 and 4, which employ dual-layer Al2O3/HfO2 GIs. These stacked GIs provide enhanced PBTS stability by simultaneously moderating H diffusion and reducing interface-related electron trapping. Notably, Device 4, with its thinner HfO2 layer, further restricts H diffusion into the IGZO channel. Such controlled H diffusion is unique to Device 4 and results in the most balanced and stable PBTS behavior among all devices examined.

Figure 7
Diagram with four panels (a-d) illustrating different devices with gate and channel configurations. (a) Device 1 uses Al₂O₃. (b) Device 2 features HfO₂. (c) Device 3 combines HfO₂ and Al₂O₃. (d) Device 4 also uses HfO₂ and Al₂O₃. Each device has a positive gate bias and shows electron flow with labeled energy levels E_C, E_F, and E_V.

Figure 7. Energy band diagrams of (a) Device 1, (b) Device 2 (c) Device 3 and (d) Device 4 under PBTS.

4 Conclusion

In this work, we demonstrate a H-regulated GI design based on a Al2O3/HfO2 stack that enables fine control over H diffusion and electron trapping in IGZO TFTs. XPS and TOF-SIMS analyses collectively reveal that H concentration and transport pathways within the GI critically determine the sign and magnitude of ΔVTH for IGZO TFTs under PBTS. The optimized IGZO TFT with 15 nm Al2O3/5 nm HfO2 GI demonstrates an exceptionally low ΔVTH of −0.02 V under PBTS at 125 °C for 104 s. Moreover, the optimized TFT exhibits excellent electrical performance, featuring a μsat of 11.61 cm2/Vs, a SS of 114 mV/dec, and a VTH of −0.23 V. These findings offer significant potential for integrated circuit applications, where excellent electrical performance and high stability are essential.

Data availability statement

The raw data supporting the conclusions of this article will be made available by the authors, without undue reservation.

Author contributions

SL: Methodology, Software, Writing – review and editing, Conceptualization, Writing – original draft, Formal Analysis, Data curation. WW: Methodology, Writing – original draft, Formal Analysis, Data curation. SZ: Software, Conceptualization, Methodology, Writing – review and editing. CW: Writing – review and editing. QX: Writing – review and editing. YL: Writing – review and editing. AS: Writing – review and editing. JK: Writing – review and editing. JJ: Methodology, Writing – original draft, Data curation, Investigation, Writing – review and editing. JZ: Conceptualization, Methodology, Supervision, Funding acquisition, Investigation, Writing – review and editing, Formal Analysis, Project administration, Writing – original draft, Data curation, Resources, Validation.

Funding

The author(s) declared that financial support was received for this work and/or its publication. This work was supported by the National Key Research and Development Program of China (Grant No. 2016YFA0301200), the Natural Science Foundation of Shandong Province (Grant No. ZR2022ZD04), the National Natural Science Foundation of China (Grant No. 62204143), and the Korea Basic Science Institute (National Research Facilities and Equipment Center), grant funded by the Ministry of Education (Grant No. 2021R1C101A405).

Conflict of interest

The author(s) declared that this work was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

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The author(s) declared that generative AI was not used in the creation of this manuscript.

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Keywords: IGZO, thin-film transistor, PBTs, high-k, dual-layer gate insulator

Citation: Lv S, Wang W, Zheng S, Wang C, Xin Q, Li Y, Song A, Kim J, Jin J and Zhang J (2025) Enhanced electrical stability of IGZO thin-film transistors using atomic layer deposited Al2O3/HfO2 dual-layer gate insulator. Front. Mater. 12:1735405. doi: 10.3389/fmats.2025.1735405

Received: 30 October 2025; Accepted: 02 December 2025;
Published: 12 December 2025.

Edited by:

Tongbo Wei, Chinese Academy of Sciences (CAS), China

Reviewed by:

Yuyao Kuang, University of California, Irvine, United States
Li Xuyang, Xi’an Technological University, China

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*Correspondence: Jidong Jin, amluamlkb25nQGhhbnlhbmcuYWMua3I=; Jiawei Zhang, Smlhd2VpLlpoYW5nQGVtYWlsLnNkdS5lZHUuY24=

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